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Verilog::Parser empty generate endgenerate #422

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veripoolbot opened this issue Nov 28, 2011 · 2 comments
Closed

Verilog::Parser empty generate endgenerate #422

veripoolbot opened this issue Nov 28, 2011 · 2 comments
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@veripoolbot veripoolbot commented Nov 28, 2011


Author Name: Walter Lavino
Original Redmine Issue: 422 from https://www.veripool.org
Original Date: 2011-11-28
Original Assignee: Wilson Snyder (@wsnyder)


Below code would generate error:

%Error: walo_001.v:8: syntax error, unexpected endgenerate

@
module any
(
// input a,
// output b,
);

generate
endgenerate

generate
// always @(*) begin
// end
endgenerate

endmodule
@

regards,
Walo

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@veripoolbot veripoolbot commented Nov 28, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-11-28T12:46:33Z


Simple enough, thanks for the report.

In git towards 3.313.

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@veripoolbot veripoolbot commented Dec 14, 2011


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2011-12-14T14:33:24Z


In 3.313.

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