Join GitHub today
GitHub is home to over 40 million developers working together to host and review code, manage projects, and build software together.Sign up
Add ability to not process some `ifdefs #426
Author Name: Chris Randall
I'd want the output to include the `ifdef LEAVE_ME line, but either include (or not) the PRE_PROCESS_ME -- I couldn't find a hook that would allow me to do in your modules -- could you point me in the correct direction, please?
I also want all includes and all defines expand -- but I suspect for maximum genericty we should consider the ability of not doing it for all of them.
Original Redmine Comment
I moved this to under Verilog-Perl, as I presume your intent is to extend vppreproc. The same thing could be done with "verilator -E" but vppreproc seems the more extendable solution.
If I understand properly there would be a new "vppreproc --keep-ifdef FOO" where all references to "
To implement this, working from the top down
Seems like a lot but shouldn't take too long as it's almost all plumbing.
Start with the git version, as I did a small refactoring to make this easier.