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Syntax error when "break" is used as block identifier for disable statement #428

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veripoolbot opened this issue Jan 5, 2012 · 1 comment
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@veripoolbot veripoolbot commented Jan 5, 2012


Author Name: Pihay Saelieo
Original Redmine Issue: 428 from https://www.veripool.org
Original Date: 2012-01-05


While reading the verilog, the following error messages are issued:
%Error: count_leading_zeroes.v:15: syntax error, unexpected "break"
%Error: count_leading_zeroes.v:16: syntax error, unexpected ';'
%Error: count_leading_zeroes.v:16: syntax error, unexpected ')', expecting ';'

Our synthesis and simulation tools can read the RTL without any problems.

Attached is a testcase that when read will reproduce the error.

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@veripoolbot veripoolbot commented Jan 12, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-01-12T00:10:31Z


break is a SystemVerilog keyword. Fix the code, or use the --language or related options to say you want only Verilog 2001.

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