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Author Name: Devendra Singh
If the net widths are declared as function of some parameters then the widths when accessed with net->width is not absolute.
Original Redmine Comment
What you describe requires elaboration, which is not something Verilog-Perl is intended to do as it requires almost full language evaluation.
See [[Manual-verilog-perl#Verilog_Perl__which_parser_package]] Which Parser Package for alternatives. I'll make it clearer there what has elaboration (Verilator and VPI).