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net widths not absolute #453

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veripoolbot opened this issue Mar 8, 2012 · 2 comments
Closed

net widths not absolute #453

veripoolbot opened this issue Mar 8, 2012 · 2 comments
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@veripoolbot veripoolbot commented Mar 8, 2012


Author Name: Devendra Singh
Original Redmine Issue: 453 from https://www.veripool.org
Original Date: 2012-03-08


If the net widths are declared as function of some parameters then the widths when accessed with net->width is not absolute.
Since a module can have any instance with different parameter values foe each instance. I would be helpful if the vector widths are absolute.
Hope I am not missing something here and not confusing a feature as an issue.

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@veripoolbot veripoolbot commented Mar 8, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-08T17:38:51Z


What you describe requires elaboration, which is not something Verilog-Perl is intended to do as it requires almost full language evaluation.

See [[Manual-verilog-perl#Verilog_Perl__which_parser_package]] Which Parser Package for alternatives. I'll make it clearer there what has elaboration (Verilator and VPI).

@veripoolbot veripoolbot closed this Mar 8, 2012
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@veripoolbot veripoolbot commented Mar 8, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-03-08T17:58:57Z


Added a FAQ there too.

@veripoolbot veripoolbot added the wontfix label Mar 14, 2020
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