Verilog::PreProc mistakenly substitute macros in numbers

[veripoolbot]

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Author Name: Wei Song
Original Redmine Issue: 502 from https://www.veripool.org
Original Date: 2012-05-01

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for the following macro definition:

`define NUMBER(d1, d2, d3)  (32'd1 + d1 + d2 + d3)

the "d1" in "32'd1" is recognised as a macro parameter.
Not sure whether it is the normal behaviour defined by specification.

[veripoolbot]

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Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-05-01T17:08:10Z

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Sorry ignore the last mail, I thought you had another define getting substituted in, not the define argument.

The spec doesn't state whitespace is needed to delimit tick defines, andt looking at some UVM and other examples I believe the behavior of substituting it in is correct.