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Verilog::PreProc mistakenly substitute macros in numbers #502
Author Name: Wei Song
for the following macro definition:
the "d1" in "32'd1" is recognised as a macro parameter.
Original Redmine Comment
Sorry ignore the last mail, I thought you had another define getting substituted in, not the define argument.
The spec doesn't state whitespace is needed to delimit tick defines, andt looking at some UVM and other examples I believe the behavior of substituting it in is correct.