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assign with value containing newline fails #507
The verilog parser would fail in case a white space is found after the 'h'
module any_logic ();
00}; // FAILS
endmodule; // any_logic
Original Redmine Comment
It's the newline, not the spaces.
The parser originally predated Verilog 1995 standard and so needs to see a complete verilog number with optional spaces. For now I fixed newlines, but this ideally requires rework to allow comments and such between the parts, and is related to fixing #�.
Newline part of fix in git towards 3.316.