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Support UVM #526

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veripoolbot opened this issue Jun 18, 2012 · 2 comments
Closed

Support UVM #526

veripoolbot opened this issue Jun 18, 2012 · 2 comments
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@veripoolbot veripoolbot commented Jun 18, 2012


Author Name: Jan Seyler
Original Redmine Issue: 526 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


It would be great for the parser to support UVM!

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@veripoolbot veripoolbot commented Jun 21, 2012


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2012-06-21T13:07:57Z


The parser at present needs to know what is a class etc when tokens are recognized. However it's easily confused when a new symbol is declared that overrides an old symbol. For example, making a variable/function of the same name of what was a class, or vice-versa. UVM confusingly (for the users) does this all over the place. For example below foo is a class, then becomes a function.

typedef class uvm_component;
class foo extends uvm_component;
function foo();
endfunction
endclass

While it might be possible to further extend the lexing, this seems a bad idea. Instead the parser needs to handle the grammar ambiguities that arise from not knowing if something is a class or not until later in the parse. This means the grammar is no longer LA(L)R but GLR. Thus the parser needs to switch to use either bison in GLR mode, or perhaps give up and go to ANTLR. ANTLR is probably better as it's a route known to work in SystemVerilog since some commercial products use it (or at least mention the ANTLR copyright, so one presumes....)

Obviously this is a great deal of work.

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@veripoolbot veripoolbot commented Dec 21, 2019


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2019-12-21T15:22:37Z


The verilog-perl parser is unlikely to be improved beyond current support. Attention is instead being given to the Verilator parser which is marching towards UVM. Or use one of the other open source parsers.

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