Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

module->net->width incorrect #65

Closed
veripoolbot opened this issue Feb 11, 2009 · 6 comments
Closed

module->net->width incorrect #65

veripoolbot opened this issue Feb 11, 2009 · 6 comments
Assignees

Comments

@veripoolbot
Copy link
Collaborator

@veripoolbot veripoolbot commented Feb 11, 2009


Author Name: Devendra Singh
Original Redmine Issue: 65 from https://www.veripool.org
Original Date: 2009-02-11
Original Assignee: Wilson Snyder (@wsnyder)


the width provided by the $net->width is incorrect
if the verilog has width declared as bigendian e.g. a verilog declaration [0:2], resultant width returned by $net->width is -1.
Width should be a absolute value and lsb and msb can provide the declaration details (endianess).

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Feb 11, 2009


Original Redmine Comment
Author Name: Devendra Singh
Original Date: 2009-02-11T10:30:13Z


Devendra Singh wrote:

the width provided by the $net->width is incorrect
if the verilog has width declared as bigendian e.g. a verilog declaration [0:2], resultant width returned by $net->width is -1.
Width should be a absolute value and lsb and msb can provide the declaration details (endianess).

I have modified files Net.pm and File.pm at my end, also I have provided the modification below contained by "#by devendra" in the line from the files below.

I have checked it with an example at my end, but not sure if it will break something else. Let me know if these are appropriate.

########################From Net.pm#############################################
sub width {
     my $self = shift;
     # Return bit width (if known)
##By devendra start
1. mma     if (defined $self->msb && defined $self->lsb) {
1. mma 	return ($self->msb - $self->lsb + 1);
1. mma     }
     if ((defined $self->msb && defined $self->lsb) && ($self->msb >= $self->lsb)) {
	return ($self->msb - $self->lsb + 1);
     }
     elsif ((defined $self->msb && defined $self->lsb) && ($self->msb < $self->lsb)) {
	return ($self->lsb - $self->msb + 1);
     }
##By devendra end
     return undef;
}
####################From File.pm######################################
sub signal_decl {
     my $self = shift;
     my $inout = shift;
     my $netname = shift;
     my $vector = shift;
     my $array = shift;
     my $signed = shift;
     my $value = shift;
     print " Sig $netname $inout\n" if $Verilog::Netlist::Debug;

     my $msb;
     my $lsb;
     if ($vector && $vector =~ /^\[(.*):(.*)\]/) {
	$msb = $1; $lsb = $2;
     } elsif ($vector && $vector =~ /^\[(.*)\]/) {
	$msb = $lsb = $1;
     }
     ##by devendra start
     else
     {$msb = $lsb = 0;}
     ##by devendra end
########################################################################################

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Feb 11, 2009


Original Redmine Comment
Author Name: Devendra Singh
Original Date: 2009-02-11T10:37:14Z


Devendra Singh wrote:

the width provided by the $net->width is incorrect
if the verilog has width declared as bigendian e.g. a verilog declaration [0:2], resultant width returned by $net->width is -1.
Width should be a absolute value and lsb and msb can provide the declaration details (endianess).

attached the files as text was not very legible.
FYI, these files are from git updated on feb 10, 2009

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Feb 11, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-02-11T19:10:18Z


Thanks for the patch. I used abs() in the first place you pointed out. This is in git, and will be in the next release.

I'm confused about the second part of your patch (lsb=msb=0). I suspect you did that to avoid a undef warning. Undefs are important to disambiguate "wire x" from "wire [0:0] x", so you need to test for undef yourself.

P.S. Since you said you grabbed from git: "git diff" will give you a file you can send so you don't need to manually track the changes.

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Feb 12, 2009


Original Redmine Comment
Author Name: Devendra Singh
Original Date: 2009-02-12T05:42:18Z


Devendra Singh wrote:

the width provided by the $net->width is incorrect
if the verilog has width declared as bigendian e.g. a verilog declaration [0:2], resultant width returned by $net->width is -1.
Width should be a absolute value and lsb and msb can provide the declaration details (endianess).

since width is calculated only if lsb and msb are defined, the width comes as undef for nets with width 1. I am from hardware design background and do not understand correctly...how will it effect if
wire x and wire [0:0] x
are treated the same way i.e. width 1 as both have width 1.

Also I believe parameters are treated as nets in Verilog-Perl and if a parameter is declared as integer then its lsb and msb should be undef, and there should be a difference in treatment for a port/wire and parameter.
Let me know if you think otherwise.

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Feb 12, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-02-12T21:48:59Z


I see your point. I changed ->width to return 1/8/16/32/64 as appropriate for the net type, when it is known and simple, else undef as before.

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Feb 26, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-02-26T11:56:33Z


In 3.120

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
2 participants
You can’t perform that action at this time.