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Module.pm ports_ordered() seems to return an array of port names and not references. #66

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veripoolbot opened this issue Feb 16, 2009 · 4 comments
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@veripoolbot veripoolbot commented Feb 16, 2009


Author Name: Nicky Ayoub
Original Redmine Issue: 66 from https://www.veripool.org
Original Date: 2009-02-16
Original Assignee: Wilson Snyder (@wsnyder)


I'm not sure if it's me or my interpretation of the docs.
From Modules.pm :

$self->ports_ordered
            Returns list of references to Verilog::Netlist::Port in the order
            the ports were declared in the module’s port list.


I replaced show_module_names() of vier with :

sub show_module_names {
     my $nl = shift;
     my $fh = shift;
     foreach my $mod ($nl->modules_sorted) {
	print $fh "  ",$mod->name,"\n";
	my @ports = $mod->ports_ordered();
	print Dumper(\@ports);
	foreach my $sig (@ports) {
	    my $net = $sig->net;
	    if ( $net->width ) {
		printf ("     %sput %s [%s:%s];\n", $sig->direction, $sig->name, $net->msb, $net->lsb,);
	    } else {
		printf ("     %sput %s\n", $sig->direction, $sig->name);
	    }
	}
     }
}

The results look like this :

% ./v2sp  --nomissing --modules memory_mask.v 
Version : 3.110
  memory_mask
$VAR1 = [
           'Q',
           'CLK',
           'CEN',
           'WEN',
           'A',
           'D',
           'OEN'
         ];
Can't locate object method "net" via package "Q" (perhaps you forgot to load "Q"?) at ./v2sp line 183.

I was expecting a port reference and not a port name in $sig.

Please comment and I can supply a patch either to the docs or the code.

Thanks,

Nicky

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@veripoolbot veripoolbot commented Feb 17, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-02-17T00:02:41Z


Hmm, yes. I think I'd prefer to change the documentation to say it returns text references, as that preserves backward compatibility, and also at the time that list is made the references don't exist yet. I think find_port_by_index be used if you really want the reference.

Sound ok?

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@veripoolbot veripoolbot commented Feb 17, 2009


Original Redmine Comment
Author Name: Nicky Ayoub
Original Date: 2009-02-17T14:37:12Z


Sounds fine. Thanks once again.

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@veripoolbot veripoolbot commented Feb 17, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-02-17T18:12:52Z


The docs are fixed in git and will be in the next release.

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@veripoolbot veripoolbot commented Feb 26, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-02-26T11:56:19Z


In 3.120

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