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syntax error in IEEE mintypmax_expression #671
I got an issue when the parser reads a mintypmax expression.
Such a parameter definition makes the parser to report a syntax error:
$ vhier mytest.v
However, if the mintypmax expression is surround by brackets, it is OK:
I checked in the documentation regarding Verilog syntax and it is seems it is not mandatory to surround by brackets the mintypmax expressions in parameter definitions. I tried to invoke vhier with --language option set to '1800-2012' and I got the same error.
I am working on Verilog models from third parties I can not modify.