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$root and package import #744

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veripoolbot opened this issue Apr 17, 2014 · 4 comments
Closed

$root and package import #744

veripoolbot opened this issue Apr 17, 2014 · 4 comments

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@veripoolbot veripoolbot commented Apr 17, 2014


Author Name: Luka Bodrozic
Original Redmine Issue: 744 from https://www.veripool.org
Original Date: 2014-04-17


Hi,
Poking around, it seems that SystemVerilog is supported rather robustly. I am having a few issues that I think might require an update.

First, wildcard importing does not seem to be supported.
I get this error:
%Error: densemem_io/dv/testbench/dm_io_stack_tb.sv:14: syntax error, unexpected IDENTIFIER, expecting PACKAGE-IDENTIFIER or STRING
For this code:
import uvm_pkg::*;

Also having some issues with hierarchies that start at $root. This code:
assign cpuif[0].hclk = $root.dm_io_stack_tb.I_io_slab.Idm_io_aux.I8.HCLK;
Fails like this:
%Error: densemem_io/dv/testbench/dm_io_stack_tb.sv:120: syntax error, unexpected $root, expecting TYPE-IDENTIFIER

Not even sure if the second one is even SV, but I think it is.

Thanks,
-Luka

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@veripoolbot veripoolbot commented Apr 17, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-17T18:31:27Z


  1. SystemVerilog requires you to declare packages before they are used. This error suggests you haven't done that.

  2. Probably a fallout of #1 above. $root should work, but isn't very common so might have bugs. If your case still fails, perhaps you could look at the grammar in src/VParseBison.y and attempt a fix?

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@veripoolbot veripoolbot commented Apr 17, 2014


Original Redmine Comment
Author Name: Luka Bodrozic
Original Date: 2014-04-17T20:23:48Z


Yep. Was going to reply. My scripts that use Verilog-Perl were misbehaving.

I'll get that fixed up, and dig into the $root thing if it still exists. Feel free to close this as a non-issue though.

Thanks,
-Luka

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@veripoolbot veripoolbot commented May 18, 2014


Original Redmine Comment
Author Name: Alex Rodionov
Original Date: 2014-05-18T06:28:49Z


Does the package need to be declared within the same file, though? Usually when using other EDA tools, the package declaration sits in a separate .sv file, and is referenced by other .sv files that include that package. Comparing and contrasting with modules: When I instantiate a ModuleA inside module ModuleB in moduleb.sv, I'm allowed to have the declaration of ModuleA in modulea.sv. Why is the same not true for package importing?

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@veripoolbot veripoolbot commented May 18, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-18T11:33:11Z


Closing as the fundamental issue was already fixed.

Does the package need to be declared within the same file, though?

Certainly not. If a package reference is failing, probably you are including or specifying the package file to your simulator but not Verilog-perl.

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