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Verilog::Preproc doe not sustitute module type in instance. #751

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veripoolbot opened this issue Apr 29, 2014 · 3 comments
Closed

Verilog::Preproc doe not sustitute module type in instance. #751

veripoolbot opened this issue Apr 29, 2014 · 3 comments

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@veripoolbot veripoolbot commented Apr 29, 2014


Author Name: Tim Jordan
Original Redmine Issue: 751 from https://www.veripool.org
Original Date: 2014-04-29


Here's in:
`define LOWER lower

`define IF_UPB_BUS_REV if_upb_bus_v2c0

module #�
(
output logic o,
input logic i
);

`IF_UPB_BUS_REV.slave bus;

`LOWER ( .o, .i );

ifdef UPPER UPPER ( o, i );
`endif

endmodule:#�

and here's out:
[jordant@helium #�] % ./#�.pl #�.sv
ticDefine : 'LOWER' 'lower' ''
ticDefine : 'IF_UPB_BUS_REV' 'if_upb_bus_v2c0' ''
`line 1 "#�.sv" 1

module #�
(
output logic o,
input logic i
);

`IF_UPB_BUS_REV.slave bus;

`LOWER ( .o, .i );

endmodule:#�

`line 21 "#�.sv" 2

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@veripoolbot veripoolbot commented Apr 29, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-29T20:34:54Z


Obviously the preprocessor doesn't care about modules or not, so it's extremely unlikely to be a bug in Verilog-Perl. Please check your script carefully; you didn't provide #�.pl; perhaps it is not actually defining anything since you must be overloading something to have it print "ticDefine".

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@veripoolbot veripoolbot commented Apr 29, 2014


Original Redmine Comment
Author Name: Tim Jordan
Original Date: 2014-04-29T22:22:39Z


Found the problem. My bad.
Thank you for your support.

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@veripoolbot veripoolbot commented Apr 29, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-04-29T22:27:51Z


Great!

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