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Verilog::Netlist errors on modport after old sytle / non-ANSI portlist #777
Author Name: Joe D
Original Assignee: Wilson Snyder (@wsnyder)
Declaring my module as below causes the tool to fail with the following error:
module myMod(clk, foo_if);
I readily see this example parsing a file with vhier. ANSI-style declarations of the equivalent code seem to work fine.
Original Redmine Comment
Partially fixed in git towards 3.404:
my_interface.mp_a foo_if ();
now works. Verilog-Perl presently requires the parenthesis in non-ANSI interfaces so it can disambiguate it from a variable declaration. Fixing the non-parenthesis version will be a major rework I unfortunately can't undertake at the moment.