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Verilog::Netlist errors on modport after old sytle / non-ANSI portlist #777

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veripoolbot opened this issue May 27, 2014 · 2 comments
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@veripoolbot veripoolbot commented May 27, 2014


Author Name: Joe D
Original Redmine Issue: 777 from https://www.veripool.org

Original Assignee: Wilson Snyder (@wsnyder)


Declaring my module as below causes the tool to fail with the following error:
%Error: syntax error, unexpected '.', expecting '('

module myMod(clk, foo_if);
input clk;
my_interface.mp_a foo_if; // <-- error parsing this line
...
endmodule;

I readily see this example parsing a file with vhier. ANSI-style declarations of the equivalent code seem to work fine.

Thanks!

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@veripoolbot veripoolbot commented May 31, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-05-31T13:53:25Z


Partially fixed in git towards 3.404:

my_interface.mp_a foo_if ();

now works. Verilog-Perl presently requires the parenthesis in non-ANSI interfaces so it can disambiguate it from a variable declaration. Fixing the non-parenthesis version will be a major rework I unfortunately can't undertake at the moment.

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@veripoolbot veripoolbot commented Sep 8, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-09-08T01:24:44Z


Closing due to age of bug, partially fixed earlier - see comments.

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