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I am having some issues with port widths for ports defined using Verilog 2001 syntax. Basically if the port has a defined width (i.e. is not a single bit) then all is well, but if it is a single bit port defined after another bus port, the single bit port seems to take the width of the previous bus port. e.g.
using $port->net->dump on ADCCLK you can see that the port is defined with a width of 12. e.g.
Net:ADCCLK I DeclT:port NetT: DataT:[11:0] Array: 11:0
However if you declare ADCCLK first then ADCCLK has the correct width defined. e.g.
Net:ADCCLK I DeclT:port NetT: DataT: Array:
Re-ordering ports connections isn't really a solution so I was wondering if there was a way round this issue? Can you specify which Verilog syntax is being used (e.g. Verilog 2001) before loading the module?
Many thanks for your help.
Original Redmine Comment
Please note that Wilson has already provided a solution for me:
Please try the following patch and let me know if you have other issues.