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Port width issue - v3.201 #80

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veripoolbot opened this issue May 1, 2009 · 2 comments
Closed

Port width issue - v3.201 #80

veripoolbot opened this issue May 1, 2009 · 2 comments
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@veripoolbot veripoolbot commented May 1, 2009


Author Name: Derek Johnstone
Original Redmine Issue: 80 from https://www.veripool.org
Original Date: 2009-05-01
Original Assignee: Wilson Snyder (@wsnyder)


I am having some issues with port widths for ports defined using Verilog 2001 syntax. Basically if the port has a defined width (i.e. is not a single bit) then all is well, but if it is a single bit port defined after another bus port, the single bit port seems to take the width of the previous bus port. e.g.

module TEST
(
output [11:0] DACL_DATA,
output ADCCLK
);

endmodule

using $port->net->dump on ADCCLK you can see that the port is defined with a width of 12. e.g.

Net:ADCCLK I DeclT:port NetT: DataT:[11:0] Array: 11:0
Net:DACL_DATA I DeclT:port NetT: DataT:[11:0] Array: 11:0

However if you declare ADCCLK first then ADCCLK has the correct width defined. e.g.

Net:ADCCLK I DeclT:port NetT: DataT: Array:
Net:DACL_DATA I DeclT:port NetT: DataT:[11:0] Array: 11:0

Re-ordering ports connections isn't really a solution so I was wondering if there was a way round this issue? Can you specify which Verilog syntax is being used (e.g. Verilog 2001) before loading the module?

Many thanks for your help.

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@veripoolbot veripoolbot commented May 1, 2009


Original Redmine Comment
Author Name: Derek Johnstone
Original Date: 2009-05-01T09:02:02Z


Please note that Wilson has already provided a solution for me:

From: Wilson Snyder wsnyder@wsnyder.org
To: derek_johnstone9@yahoo.co.uk
Sent: Wednesday, 29 April, 2009 21:25:34
Subject: Re: Verilog-Perl-3.201 issue

firstly many thanks
for your Verilog perl module (v3.201), I am using it at the moment and it is excellent.
However I am having some issues with port widths for ports defined using Verilog
2001 syntax. Basically if the port has a defined width (i.e. is not a single
bit) then all is well, but if it is a single bit port defined after another bus
port, the single bit port seems to take the width of the previous bus port.
e.g.

Please try the following patch and let me know if you have other issues.

-Wilson

Index: Parser/VParseBison.y
===================================================================
--- Parser/VParseBison.y        (revision 76448)
+++ Parser/VParseBison.y        (working copy)
@@ -723,8 +723,10 @@

portDirNetE:                  // IEEE: part of port, optional net type and/or direction
                 /* empty */                            { }
-      |      port_direction                          { }
-      |      port_direction net_type                { } // net_type calls VARNET
+      //                      // Per spec, if direction given default the nettype.
+      //                      // The higher level rule may override this VARTYPE with one later in the parse.
+      |      port_direction                          { VARTYPE(""/*default_nettype*/); }
+      |      port_direction net_type                { VARTYPE(""/*default_nettype*/); } // net_type calls VARNET
         |      net_type                                { } // net_type calls VARNET
         ;

@@ -1027,7 +1029,7 @@
         |      port_directionDecl port_declNetE yVAR implicit_type { VARTYPE($4); } list_of_variable_decl_assignments  { }
         |      port_directionDecl port_declNetE signingE rangeList { VARTYPE(SPACED($3,$4)); } list_of_variable_decl_assignments      { }
         |      port_directionDecl port_declNetE signing            { VARTYPE($3); } list_of_variable_decl_assignments  { }
-      |      port_directionDecl port_declNetE /*implicit*/      {/*VARTYPE-same*/} list_of_variable_decl_assignments        { }
+      |      port_directionDecl port_declNetE /*implicit*/      { VARTYPE("");/*default_nettype*/} list_of_variable_decl_assignments        { }
         ;

tf_port_declaration:          // ==IEEE: tf_port_declaration
@@ -2318,7 +2320,7 @@
         |      yVAR data_type                          { VARTYPE($2); }
         |      yVAR implicit_type                      { VARTYPE($2); }
         //
-      |      tf_port_itemDir /*implicit*/            { /*same type as last-see spec*/ }
+      |      tf_port_itemDir /*implicit*/            { VARTYPE(""); /*default_nettype-see spec*/ }
         |      tf_port_itemDir data_type              { VARTYPE($2); }
         |      tf_port_itemDir signingE rangeList      { VARTYPE(SPACED($2,$3)); }
         |      tf_port_itemDir signing                { VARTYPE($2); }

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@veripoolbot veripoolbot commented May 1, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-01T13:32:54Z


Thanks for bugging this.

I fixed this and just pushed version 3.202 now, since this was a fairly serious problem.

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