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Old version problem #801

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veripoolbot opened this issue Jul 9, 2014 · 2 comments
Closed

Old version problem #801

veripoolbot opened this issue Jul 9, 2014 · 2 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jul 9, 2014


Author Name: Am A
Original Redmine Issue: 801 from https://www.veripool.org
Original Date: 2014-07-09


The Verilog-Perl tool processes the attached file with the following errors:

quote_zero.sv:14:Unknown symbol, ignoring to eol: '0;
quote_zero.sv:15:Unknown symbol, ignoring to eol: '1;

I tried this out in QuestaSim, and it's building there.

Thanks!

Here's a copy of the file for reference, if it's helpful:

module quote_zero
(
     input logic i_clock,
     input logic i_reset,

     output logic [9:0] o_flag_a,
     output logic [9:0] o_flag_b
);

always_ff @(posedge i_clock)
begin
     if (i_reset)
     begin
         o_flag_a <= '0; 
         o_flag_b <= '1; 
     end 
     else
     begin
         o_flag_a <= o_flag_a + 1;
         o_flag_b <= o_flag_b - 1;
     end 
end

endmodule

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@veripoolbot veripoolbot commented Jul 9, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-07-09T12:06:41Z


There is support for all of system verilog so '0 should work fine. I run your example "vhier --cells quote_zero.sv" and it works, so I'm not seeing what is wrong. Does this work for you? Are you sure you're running the latest version (although this should have been working for years)?

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@veripoolbot veripoolbot commented Jul 10, 2014


Original Redmine Comment
Author Name: Am A
Original Date: 2014-07-10T00:29:35Z


My apologies, you're absolutely correct. I had an issue with an old version of the Verilog::Language library being referenced unexpectedly. This works correctly on the newest version.

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