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Old version problem #802

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veripoolbot opened this issue Jul 9, 2014 · 2 comments
Closed

Old version problem #802

veripoolbot opened this issue Jul 9, 2014 · 2 comments

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@veripoolbot
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@veripoolbot veripoolbot commented Jul 9, 2014


Author Name: Am A
Original Redmine Issue: 802 from https://www.veripool.org
Original Date: 2014-07-09


If I declare and instantiate an interface as in the attached files, then Verilog::Netlist gives the following errors:

%Error: my_if.sv:17: Signal declaration outside of module definition
%Error: my_if.sv:17: Signal declaration outside of module definition
%Error: my_if.sv:17: Signal declaration outside of module definition
%Error: my_if.sv:25: Signal declaration outside of module definition
Exiting due to errors

I'm going to take a guess and say that passing the interface through two modules causes the error. Without the second module (another_module), the errors no longer appear.

Sorry for the simplistic example. Please let me know if there are any issues with it.

If it helps, the example compiles and simulates fine in QuestaSim.

Thanks!

Here are the files for reference:

`timescale 1ns / 1ps 
interface my_if
(
     input logic i_clock,
     input logic i_reset
);

     logic i_signal, o_signal;

     assign i_signal = o_signal;

     modport first_port (
         input
             i_clock,
             i_reset,
             i_signal
     );

     modport second_port (
         input
             i_clock,
             i_reset,
         output
             o_signal
     );

endinterface: my_if

`timescale 1ns / 1ps
module interface_test
(
     input logic i_clock,
     input logic i_reset,

     my_if.first_port m_first,
     my_if.second_port m_second
);
     
     another_module
     u_am
     (
         .i_clock(i_clock),
         .i_reset(i_reset),

         .m_first(m_first)
     );

endmodule

`timescale 1ns / 1ps
module another_module
(
     input logic i_clock,
     input logic i_reset,

     my_if.first_port m_first
);

endmodule

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@veripoolbot veripoolbot commented Jul 9, 2014


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2014-07-09T12:09:32Z


There is support for all of system verilog so this should work fine. I run your example and it works. Your problem is probably identical to #�, whatever that is.

./vhier +libext+.sv -y . --cells interface_test.sv
interface_test
my_if
my_if
another_module
my_if

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@veripoolbot veripoolbot commented Jul 10, 2014


Original Redmine Comment
Author Name: Am A
Original Date: 2014-07-10T00:42:23Z


As in "#�":http://www.veripool.org/issues/801-Verilog-Perl-Verilog-Netlist-doesn-t-recognize-1-or-0-syntax, my issue was a problem referencing the correct Verilog::Language library. The linked example doesn't exhibit the behavior above in the newest version. Sorry for the false report.

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