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Possible error in precompiler macro parser #84
Hi, I have a question regarding the precompiler macro parser.
If I'm not mistaken, Verilog-Parser doesn't support newline characters to separate formal arguments. Ex:
Again, if I'm not mistaken I think this is valid syntax.
According to the Verilog-2005 LRM (IEEE Std 1364-2005), on section 19.3.1 (page 351 first parragraph) "The formal argument names shall be simple_identifiers, separated by commas and optionally whitespace". Focus on the optional whitespaces. Now in the same document of the formal syntax definition (Annex A), on section A.9.4 (page 509) whitespaces are defined in BNF as:
So, if this syntax is valid, could it be included on Verilog-Perl?
Original Redmine Comment
Wow, the committee botched that one. It should be the same rule as CPP,
This is somewhat a pain to fix as it reads the entire line right now, so no patch yet.