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Possible error in precompiler macro parser #84

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veripoolbot opened this issue May 8, 2009 · 4 comments
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Possible error in precompiler macro parser #84

veripoolbot opened this issue May 8, 2009 · 4 comments
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@veripoolbot veripoolbot commented May 8, 2009


Author Name: David A
Original Redmine Issue: 84 from https://www.veripool.org
Original Date: 2009-05-08
Original Assignee: Wilson Snyder (@wsnyder)


Hi, I have a question regarding the precompiler macro parser.

If I'm not mistaken, Verilog-Parser doesn't support newline characters to separate formal arguments. Ex:

`define MY_MACRO ( FORMAL1, // here is a newline char, which is also a whitespace
                   FORMAL2 ) rest of the macro text here...

Again, if I'm not mistaken I think this is valid syntax.

According to the Verilog-2005 LRM (IEEE Std 1364-2005), on section 19.3.1 (page 351 first parragraph) "The formal argument names shall be simple_identifiers, separated by commas and optionally whitespace". Focus on the optional whitespaces. Now in the same document of the formal syntax definition (Annex A), on section A.9.4 (page 509) whitespaces are defined in BNF as:

 white_space ::= space | tab | newline | eof

So, if this syntax is valid, could it be included on Verilog-Perl?

Thanks,
Davd

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@veripoolbot veripoolbot commented May 8, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-08T23:59:09Z


Forgot to mention, I'm using Verilog-Pearl 3.202, on Linux SLES 9

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@veripoolbot veripoolbot commented May 9, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-09T00:14:01Z


Wow, the committee botched that one. It should be the same rule as CPP,
and it's definitely illegal there, but I see at least one simulator takes
it so your interpretation is correct. If I were you I'd change the code
and never do that again, as you're certain to hit other tools that will get this wrong.

This is somewhat a pain to fix as it reads the entire line right now, so no patch yet.

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@veripoolbot veripoolbot commented May 11, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-11T15:58:49Z


Fixed in the git versions of Verilog-Perl and Verilator, will be in next releases.

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@veripoolbot veripoolbot commented May 19, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-19T14:16:45Z


In 3.210

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