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Can't locate object method "new_cell" via package "Verilog::Netlist::Interface" #87

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veripoolbot opened this issue May 12, 2009 · 12 comments
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@veripoolbot veripoolbot commented May 12, 2009


Author Name: David A
Original Redmine Issue: 87 from https://www.veripool.org
Original Date: 2009-05-12
Original Assignee: Wilson Snyder (@wsnyder)


Hi, I have a problem with vhier, I havent prepared a testcase to upload yet, lets hope the testcase is not necessary.

I'm using vhier to generate the hierachy of a SystemVerilog small design. The top level module receives (in its port-list) several signals as well as several interfaces (system verilog interface). So I'm including (`include) all the interface definition files at the top of the file that contains the top level module (so that the "datatypes" of the interfaces are known by the parser once it reaches the port-list of the top level module).

vhier generates the following error:

Can't locate object method "new_cell" via package "Verilog::Netlist::Interface" at /usr/lib/perl5/x86_64-linux-thread-multi/Verilog/Netlist/File.pm line 238, line 94.

Line 238 of File.pm actually calls new_cell, but I'm not sure what the line 94 is referring to.

Thanks,
David

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@veripoolbot veripoolbot commented May 12, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-12T17:55:46Z


I thought I had fixed this as I saw it and fixed it with the test case in your other issue. Are you using the fixed git version?

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-13T02:23:42Z


No I'm not. I had not used git before, and for some reason I can't check out the project from the repository.

git clone http://git.veripool.org/git/Verilog-Perl temp/Verilog-Perl/
Initialized empty Git repository in temp/Verilog-Perl/.git/
Cannot get remote repository information.
Perhaps git-update-server-info needs to be run there?

git --version
git version 1.5.3.rc5.

Is there any other way to get the latest working version without using git?

Thanks
David

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-13T11:16:03Z


I's worth trying to get git working, as the patch is large and given you found two issues more are possible.

First, my version of git doesn't like paths in the second argument (ie use Verilog-Perl not temp/Verilog-Perl/) but I think you're beyond that.

Perhaps you're at work, and need a proxy? Ask your IT person. Or look in Firefox (for example) for the settings - you can see them in Options->Advanced->Network->Settings

Then

export http_proxy=http://:@<proxy_ip>:<proxy_port>

where:

username = your network username (someuser)
password = your network password (somepassword)
proxy_ip = the ip address of your proxy server (192.168.1.1)
proxy_port = the port number for the proxy (80)

the full string would look like this:

export http_proxy=http://someuser:somepassword@192.168.1.1:80

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-13T16:59:42Z


Thanks, I've downloaded the git HEAD version. Is there a way other than editing the Makefile manually to specify a different install dir? (like the makepl_arg configuration parameter for CPAN installation)?

Thanks
David

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-13T17:28:59Z


Nevermind, it seems
perl Makefile.PL INSTALL_BASE=/path/to/your/home/dir
works just fine.

Thanks.

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-13T17:43:24Z


Ok, I'm using the latest git version, and I'm still getting the same error.

Can't locate object method "new_cell" via package "Verilog::Netlist::Interface" at /home/darditti/lib/perl5/x86_64-linux/Verilog/Netlist/File.pm line 238, line 94.

Any ideas?

Thanks,
David

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-13T17:50:25Z


Hmm, guess it's a different case from the other I fixed, sorry thought that would do it. I suspect there's something in the interface declaration that's confusing it, can you send it along?

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-13T20:48:12Z


I've isolated the issue, no testcase though I think its simple enough.

The problem is caused by interfaces receiving other interfaces on their port-list. e.g:

// first interface. Parses Ok
interface intf1 ();
   // blah...
   modport intf2_mp ( .... );
   // blah...
endinterface


// Second interface, receives first in port-list. Parser error.
interface intf2 (
   input bit       clk,
   input bit       arst,
   intf1.intf2_mp  myintf,
);
   // more blah...
endinterface

This is exactly what I've got, a second interface receiving a first interface on it's port-list specifying the modport (intf1.intf2_mp).

If I'm not mistaken, according to 1800-2005 Std (section A - Formal Syntax) this is allowed, as I understand the interface port-list has the same restrictions as the module port-list.

Thanks again,
David

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-13T21:18:20Z


Didn't know that was possible; yes I can make a test case easily. I'll fix it.

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@veripoolbot veripoolbot commented May 13, 2009


Original Redmine Comment
Author Name: David A
Original Date: 2009-05-13T22:37:37Z


Thanks a lot.

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@veripoolbot veripoolbot commented May 14, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-14T14:45:20Z


This is fixed in the GIT version and will be in the next release.

BTW if you'd like to share your last name, I'll give you proper credit in the Changes.

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@veripoolbot veripoolbot commented May 19, 2009


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2009-05-19T14:16:23Z


In 3.210

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