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Are there any plans to implement AST in Verilog-Perl? #88
Original Redmine Comment
From the docs:
"Abstract Syntax Tree
Verilog::Parser knows enough to make a complete Abstract Syntax Tree (AST) of Verilog syntax, however this hasn't been implemented yet. This would allow any arbitrary transformation of Verilog syntax (everthing is known excluding whitespace). If you'd find this useful please contact the author."
It's not obvious what the format should be. You'll need to say what you're interested in.