Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

verilot_text does not output complete defparams #967

Closed
veripoolbot opened this issue Sep 23, 2015 · 2 comments
Closed

verilot_text does not output complete defparams #967

veripoolbot opened this issue Sep 23, 2015 · 2 comments
Labels

Comments

@veripoolbot
Copy link
Collaborator

@veripoolbot veripoolbot commented Sep 23, 2015


Author Name: Christian Fibich
Original Redmine Issue: 967 from https://www.veripool.org


When I try to P&R a VQM netlist exported by Verilog::Perl in Quartus,
I get the following error message for (approximately) every @defparam@ statement

P&R of the original netlist works fine.

Setup:

  • Verilog::Perl from git (@f569a8c vrename quote tests@)
  • Quartus II 13.0
  • Synplify Pro

Minimal example (see attached script):

  1. Synthesize HDL design with Synplify for Altera, using VQM as netlist format
  2. Load generated netlist in Verilog::Perl
  3. Export netlist out of Verilog::Perl via using @$nl->verilog_text()@
  4. (Try to) compile exported VQM netlist in Quartus

An obvious fix would concern the @verilog_text@ method in Netlist/Module.pm.
There, we would need to output the matching Verilog::Netlist::Defparam statements
in the loop through all instantiated cells.

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented Sep 23, 2015


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2015-09-23T13:16:34Z


verilog_text was not intended to work with RTL, so as you noted defparam and many other statements will not be preserved.

If you'd like to provide a patch to improve this process we'll be glad to take it.

@veripoolbot

This comment has been minimized.

Copy link
Collaborator Author

@veripoolbot veripoolbot commented May 17, 2017


Original Redmine Comment
Author Name: Wilson Snyder (@wsnyder)
Original Date: 2017-05-17T01:39:59Z


Closing due to age.

Sign up for free to join this conversation on GitHub. Already have an account? Sign in to comment
Projects
None yet
Linked pull requests

Successfully merging a pull request may close this issue.

None yet
1 participant
You can’t perform that action at this time.