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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity cpld is
generic (
g_test_mode : boolean := false
);
port (
column_from_cpu_clk : in std_logic;
column_from_cpu_data : in std_logic;
row_from_cpu_clk : in std_logic;
green_row_from_cpu_data : in std_logic;
red_row_from_cpu_data : in std_logic;
row_enable_from_cpu : in std_logic;
from_button : in std_logic_vector(4 downto 0);
green_row_to_leds : out std_logic_vector(7 downto 0);
red_row_to_leds : out std_logic_vector(7 downto 0);
column_to_leds : out std_logic_vector(15 downto 0);
button_to_cpu : out std_logic_vector(2 downto 0)
);
end entity;
architecture hdl of cpld is
constant button_up : std_logic_vector(4 downto 0) := "11100";
constant button_left : std_logic_vector(4 downto 0) := "10110";
constant button_right : std_logic_vector(4 downto 0) := "11001";
constant button_down : std_logic_vector(4 downto 0) := "10011";
constant button_centre : std_logic_vector(4 downto 0) := "01111";
signal column_data : std_logic_vector(column_to_leds'range) := (0 => '1', others => '0');
begin
column_gen : for ix in column_to_leds'range generate
column_to_leds(ix) <= '0' when column_data(ix) = '1' else 'Z';
end generate;
runtime_gen : if not g_test_mode generate
signal green_row_data : std_logic_vector(green_row_to_leds'range) := (others => '0');
signal red_row_data : std_logic_vector(red_row_to_leds'range) := (others => '0');
begin
green_row_to_leds <= green_row_data when row_enable_from_cpu = '1' else (others => '0');
red_row_to_leds <= red_row_data when row_enable_from_cpu = '1' else (others => '0');
row_data_p : process (row_from_cpu_clk)
begin
if rising_edge(row_from_cpu_clk) then
green_row_data <= green_row_data(green_row_data'high-1 downto green_row_data'low) & green_row_from_cpu_data;
red_row_data <= red_row_data(red_row_data'high-1 downto red_row_data'low) & red_row_from_cpu_data;
end if;
end process;
column_shift_p : process(column_from_cpu_clk)
begin
if rising_edge(column_from_cpu_clk) then
column_data <= column_data(column_data'high-1 downto column_data'low) & column_from_cpu_data;
end if;
end process;
with from_button select button_to_cpu <=
"001" when button_up, -- up
"011" when button_left, -- left
"100" when button_right, -- right
"110" when button_down, -- down
"111" when button_centre, -- centre
"000" when others;
end generate;
column_test_gen : if g_test_mode generate
signal right_detect : std_logic := '0';
signal right_detect_1d : std_logic := '0';
signal up_detect : std_logic := '0';
signal up_detect_1d : std_logic := '0';
signal centre_detect : std_logic := '0';
signal osc : std_logic := '0';
signal row_data : std_logic_vector(red_row_to_leds'range) := (0 => '1', others => '0');
begin
green_row_to_leds <= row_data;
red_row_to_leds <= row_data;
button_to_cpu <= (others => '0');
button : process(osc)
begin
if rising_edge(osc) then
if from_button = button_right then
right_detect <= '1';
centre_detect <= '0';
up_detect <= '0';
elsif from_button = button_up then
right_detect <= '0';
centre_detect <= '0';
up_detect <= '1';
elsif from_button = button_left or from_button = button_down then
right_detect <= '0';
centre_detect <= '0';
up_detect <= '0';
elsif from_button = button_centre then
right_detect <= '0';
centre_detect <= '1';
up_detect <= '0';
end if;
end if;
end process;
col : process(osc)
begin
if rising_edge(osc) then
right_detect_1d <= right_detect;
up_detect_1d <= up_detect;
if right_detect = '1' and right_detect_1d = '0' then
column_data <= column_data(column_data'high-1 downto column_data'low) & column_data(column_data'high);
elsif up_detect = '1' and up_detect_1d = '0' then
row_data <= row_data(row_data'high-1 downto row_data'low) & row_data(row_data'high);
end if;
end if;
end process;
cpld_osc_altufm_osc_iu7_1 : entity work.cpld_osc_altufm_osc_iu7
port map (
osc => osc,
oscena => '1');
end generate;
end architecture;