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This repository includes FPGA IP Blocks compatible with the Arduino Vidor family of products and is aimed to users already familiar with FPGA development process. FPGA development using native tools, although encouraged, is not supported by Arduino as it is quite complex difficult to support. If you feel this challenge is for you please know that we can only provide very limited support as our main efforts will be targeted at providing a smooth experience within Arduino IDE and Arduino Create through precompiled libraries and with the web tool that will provde an easy way to assemble IP blocks.

Directory structure

directory structure is summarized in the following table:

Directory Contents
ip source code for IP blocks
projects sample project files for the various boards
constraints constraint files for the various boards. includes pinout and timings

Things to know before getting started

Once again this repository is intended only for people already familiar with FPGA programming. At the moment the primary intent is to disclose IP block functionality and present the infrastructure we created so that potantial contributors can start to evaluate it. As of today this repository does not contain full source code required to compile the released libraries as parts of it requires some more polishing both in terms of code and in terms of licensing (in some cases from third parties). Full examples of working FPGAs, along with instructions to create a library and access the FPGA, will be posted here but will not necessarily reflect the official images we are publishing.

Getting started

The prerequisite to compile MKRVIDOR4000 board FPGA images is Quartus II 18.0 Lite or Standard which can be downloaded from Altera/Intel web site. Once Quartus is installed you can open a project under the projects directory and compile it with Quartus.

Quartus will produce a set of files under the output_files directory in the project folder. In order to incorporate the FPGA in the Arduino code you need to create a library and preprocess the ttf file generated by Quartus so that it contains the appropriate headers required by the software infrastructure. Details of this process will be disclosed as soon as the flow is stable.

Programming the FPGA is possible in various ways:

  1. flashing the image along with Arduino code creating a library which incorporates the ttf file
  2. programming the image in RAM through USB Blaster (this requires mounting the FPGA JTAG header). this can be done safely only when SAM D21 is in bootloader mode as in other conditions it may access JTAG and cause a contention
  3. programming the image in RAM through the emulated USB Blaster via SAM D21 (this component is pending release)


repository for Vidor FPGA IP blocks and projects







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