Use MAKE variable in Makefile

vinc · Nov 9, 2012 · 1596dd7 · 1596dd7
1 parent 432ae72
commit 1596dd7
Showing 1 changed file with 3 additions and 3 deletions.
diff --git a/Makefile b/Makefile
@@ -15,9 +15,9 @@ $(EXECUTABLE): $(OBJECTS)
 	$(CXX) $(CXXFLAGS) -c -o $@ $<
 
 test:
-	make -C ./test/unit
-	make -C ./test/unit test
+	$(MAKE) -C ./test/unit
+	$(MAKE) -C ./test/unit test
 
 clean:
 	$(RM) $(OBJECTS) $(EXECUTABLE)
-	make -C ./test/unit clean
+	$(MAKE) -C ./test/unit clean