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add MIPS architecture to GCC ethread atomics support

Gcc for MIPS supports immediate atomic gets and sets, and also
supports a working __sync_synchronize() for gcc 4.2 and greater.
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1 parent a78b39a commit 6412564cadfb99c0c2a5089f07e4a0a02f13902c @vinoski committed Sep 8, 2010
Showing with 7 additions and 2 deletions.
  1. +7 −2 erts/include/internal/gcc/ethr_atomic.h
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9 erts/include/internal/gcc/ethr_atomic.h
@@ -31,7 +31,7 @@
#define ETHR_IMMED_ATOMIC_SET_GET_SAFE__ 0
/* Enable immediate read/write on platforms where we know it is safe */
#if defined(__i386__) || defined(__x86_64__) || defined(__sparc__) \
- || defined(__powerpc__) || defined(__ppc__)
+ || defined(__powerpc__) || defined(__ppc__) || defined(__mips__)
# undef ETHR_IMMED_ATOMIC_SET_GET_SAFE__
# define ETHR_IMMED_ATOMIC_SET_GET_SAFE__ 1
#endif
@@ -48,13 +48,18 @@ typedef struct {
* a noop on at least some platforms with some gcc versions.
* This has suposedly been fixed in some gcc version, but we
* don't know from which version. Therefore, we use the
- * workaround implemented below on all gcc versions.
+ * workaround implemented below on all gcc versions except
+ * for gcc 4.2 or above for MIPS, where it's been verified.
*/
+#if defined(__mips__) && (__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 2))
+#define ETHR_MEMORY_BARRIER __sync_synchronize()
+#else
#define ETHR_MEMORY_BARRIER \
do { \
volatile long x___ = 0; \
(void) __sync_val_compare_and_swap(&x___, (long) 0, (long) 1); \
} while (0)
+#endif
#define ETHR_READ_DEPEND_MEMORY_BARRIER ETHR_MEMORY_BARRIER
#if defined(ETHR_TRY_INLINE_FUNCS) || defined(ETHR_AUX_IMPL__)

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