QA_Design Of D-Flip Flop Using Verilog_Usability_smk

[kolliSuman]

Defect Description :
In the home page/landing page of "Design Of D-Flip Flop Using Verilog" experiment, an extra header link is present in the page where the extra header link should be removed as it is not required

Actual Result :
In the home page/landing page of "Design Of D-Flip Flop Using Verilog" experiment, an extra header link is present in the page

Environment :
OS: Windows 7, Linux
Browsers: Firefox,Chrome
Bandwidth : 100Mbps
Hardware Configuration:8GBRAM ,
Processor:i5

Test Step Link:
https://github.com/Virtual-Labs/lsi-iiith/blob/master/test-cases/integration_test-cases/Design%20Of%20D-Flip%20Flop%20Using%20Verilog/Design%20Of%20D-Flip%20Flop%20Using%20Verilog_01_Usability_smk.org

Attachment:

[sadhanareddy]

issue is resolved now.

[BSravanthi]

Closed #23