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Schematics and board layouts for an Apollo Guidance Computer replica
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rburkey2005 This adds fixes to the schematics for changes identified in comparing…
… against the independent AGC

schematics in the "schematics" branch of the main Virtual AGC repository.  Changes include:  Topological
(but not logical) fixes to the DKCTR4,5,4/,5/ signals in the inout_v schematic. Wiring fix (incorrect
signal sources for 5 gates) in inout_iv. Fixed incorrect signal source (including MGOJAM output polarity)
for one gate in timer.  Fixed incorrect topology (but not logic) for 3 output signals in service_gates.
Fixed backplane signal source (MYCLMP incorrectly used everywhere in place of the correct STRT2) in
memory_timing_addressing.  ROPER, ROPES, ROPET had incorrectly omitted STRT2 as an input signal in
four_bit_2. A couple of  internal nets local to sheets were also renamed due to conflicts with analysis
software.  None of these fixes had any measurable effect on instruction execution; Validation was
passed prior to the fixes, and continues to be passed after the fixes, and the identical instruction
sequence occurs in doing so.

For me, warnings about missing components from the libraries occur upon every schematic load, though
these missing components don't seem to actually be in the circuits.  I tried to make some library
changes to work around that.  My changes don't actually fix the problem, but rather than try to back
them out and redo all the testing, they're a part of this commit as well.
Latest commit 29c5dfe Oct 29, 2018
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alarms This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
ch77_alarm_box This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
common Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
counter_cell_i This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
counter_cell_ii Power net updates for Counter Cell I+II and Inout V Nov 2, 2016
crosspoint_ii Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
crosspoint_nqi
dsky Digitized the relay matrix signal flow schematic diagram for the DSKY… Jul 10, 2017
fixed_erasable_memory
four_bit_1 Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
four_bit_2 Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
four_bit_3 Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
four_bit_4 Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
inout_i Updated Inout I to be on +4VSW Nov 1, 2016
inout_ii Updated Inout II to be on +4VSW Nov 1, 2016
inout_iii Broke out SBYREL/ for +4VSW switching Nov 2, 2016
inout_iv This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
inout_v This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
inout_vi Updated Inout VI to be on +4VSW Nov 2, 2016
inout_vii Added the CH77 alarm box (restart monitor) and switched most (all?) m… Jan 30, 2017
libs This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
memory_timing_addressing This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
parity_s_register This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
rupt_service
scaler Added power pin units to most parts, +4VDC and +4VSW power components… Oct 15, 2016
service_gates This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
sq_register
stage_branch Some initial condition updates for the CH77 alarm box and a monitor o… Mar 26, 2017
timer This adds fixes to the schematics for changes identified in comparing… Oct 29, 2018
.gitignore New (original) seven-segment decoder, taken from the Apollo 12 Missio… Nov 5, 2016
LICENSE Added a license (MIT) Sep 10, 2016
README.md Updated the README May 20, 2017

README.md

AGC Hardware

This repository contains KiCAD projects and libraries for a replica of the Apollo Guidance Computer. The schematics have, for the most part, been digitized directly from the original schematics for the computer and ND-1021042, the LEM Primary Guidance, Navigation, and Control System Manual, Volume I and Volume II. The schematics have been peppered with metadata required for digital simulation using my agc_simulation repository.

Current Status

All logic modules (A1-A24) have been digitized and appear to be operating correctly in simulation. Additionally, one custom module, fixed_erasable_memory, has been designed. The simulation is able to completely pass the AGC Block Two Self-Check present in Aurora 12 (the only program we have so far with the complete version), so the central processor wiring is correct. Interfaces still need to be fully tested.

The current focus is on designing and building a working DSKY replica, which will make further interface testing significantly easier. The digital indicator and alarm indicator modules are done, and the Indicator Driver Module has been digitized.

ND-1021042, which contains all of the schematics missing from Eldon Hall's set, has recently become available. Once the DSKY is functioning, I plan to do another pass through A1-A24 and check for differences between the schematics, ND-1021042, and my digitizations. I may or may not end up implementing accurate memory modules after that.

Differences from the Real Thing

  • Modern 74HC-series components are used due to the unavailability of RTL logic chips.
  • I've taken advantage of the nearly-infinite fanout of 74HC chips to remove all fanout expansion gates.
  • To reduce chip count, I've not limited myself to using only 3-input NOR gates; I also use NOT gates, 2-input NOR gates, and 4-input NOR gates, where applicable. Combined with the deletion of fanout expansion gates, the total chip count is roughly half of the original's.
  • Again due to the nature of 74HC logic, outputs of NOR gates cannot be directly connected together as was possible with RTL. Where this is necessary (cross-module buses and >4 input gates), I've inserted fast open-drain buffers with accompanying pullup resistors. This gives very close to the same behavior, as the fan-in expander gates of the original were operating effectively open-collector lines.
  • I've been fairly liberal about moving sections of logic around to make modules more stand-alone, and to condense related logic all into the same module. This facilited much easier development, and I anticipate it to make bench-testing individual modules easier when I've actually gotten boards manufactured. I also believe it to have significantly reduced the number of signals that will be going across the final backplane, although I have no numbers to back this up.
  • The implementation for fixed and erasable memory module is custom, by me. It replaces all Tray B modules with the exception of the analog alarms module and the clock oscillator module.
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