…6.29-kvm

Simply remove a small comment in handle_abort().

This is a rather old out-of-tree driver used with the RealView
Development Suite and the FAST models, which has been slightly adapted
to fit the 2.6.33 version of the kernel.

When injecting prefetch aborts into the guest the ARMv7 architecture now
specifies that the IFAR register should be set with the address causing
the prefetch abort.

Removed the modify_domain boolean variable.

An incorrect bitmask was used to check if an invalid bit set of the MSR
instruction was set, but this didn't manifest itself before ARMv7 at
least with the currently used guest kernels. In any case, it's fixed
here.

The ARMv7 processor handles the MSR instruction slightly different than
the ARMv6 since it is possible to modify a different set of bits in the
PSRs under certain conditions. Support is hereby introduced.

The Data processing instruction emulation is done using self-modifying
code and the move to ARMv7 requires special handling of this, which
differs from that of ARMv6. However, in the process, the code for ARMv6
could be written a little nicer, and that change is also a part of this
commit.

Both the actual handling of the TLB and caches on world-switches and the
emulation code must be adapted to work with ARMv7. This commit handles
just that.

Change the tlbflush.h functionality so that the host kernel completely
flushes the TLB when required (otherwise we break functionlity after
using nG mappings on the host) but KVM only evicts guest TLB entries on
for instance host vector switch.

Some places it spit out when hitting a specific address and so on which
are no longer relevant in any way. Die.

Instead of checking conditions when creating the VCPU we now use the KVM
general functions that checks if the host processor is compatible - I
gather this is really meant to check for virtualization extensions, but
we can use it for the ARM specifics either way.

Factor out some functionality to a header file that considers the
current implementation of cache behavior and delegates the
responsibility. Also start using the Linux macros to flush the pmd
entries when modifying shadow page tables to ensure correctness at that
end and clean up a few other places regarding cache maintenance, which
were commented out and so on.

Cleanup the stale code from the attempt to change host kernel mappings
on the fly. This is essentially a flag on the mm_struct.

Also remove the old code for setting host kernel page tables on the fly
in arch/arm/kvm/arm.c

Previous commits or'ed the nG bits with coarse 1-st level descriptors
which is horribly incorrect. This should resolve those issues and run nG
host mappings on v7.

This will allow us not to flush TLB entries on world switches.

This will allow us not to flush TLB entries on world switches.

Some code got back-merged from 2.6.33 in arch/arm/mm/context.c which has
been cleaned up and the reminicense of the dump_vcpu_... from
page_alloc.c has also been removed.

This will allow us not to flush TLB entries on world switches.

Provides some additional logging functionality and infrastructure to
place breakpoints in guest code to examine state at specifc points where
behavior varies.

Some times the host would catch an error in which the guest could not
access its own vector page even in privileged mode. This would typically
happen after switching the vector location for KVM a couple of times.

Turned out to be very simple, needed to clean caches after unmapping
addresses in the shadow page tables.

This commit is related to the 'KVM: (arm) Debug vector access and guest
bug' commit in that it fixes what the previous tries to debug and also
keeps some of the introduced functionality around although renaming it a
little bit to be more clear for future use. It will probaby go away
eventually though.

When emulating privileged data processing instructions, the instructions
may be configured to execute conditionally, and for this to work
correctly we need the CPSR cond bits to be that of the guest state when
emulating the instruction on the host side. This is in fact not used by
Linux guest versions tested so far, but it was a 'theoretical bug'.

This commit is a debugging commit, which should probably be reversed
later on or at least modified.

WARNING: This introduces complete TLB flushing on world-switches after
first guest jump to user space.

In a single place, when calling kvm_switch_host_vectors I forgot to
propagate a possible error, which could cause the 'dreaded' message
"Privileged mode cannot access vector page" since the error deludes a
TLB flush, which is highly necessary.

When the VCPU changes between privileged and user mode, the access
permission bits must change on the shadow page tables, since they are
adapted for running always in user mode. Until now, we have simply
invalidated the entire shadow page table when this happened causing
quite a performance degredation when the guest started running in user
space and issuing system calls.

This commit introduces a new routine, which scans the shadow page table
and for each entry find the corresponding guest entry and re-calculates
the correct page table entries.

Since this reads guest page tables several times, it's too expensive to
clean caches on each run. Instead, we move the cache cleaning when
reading shadow page tables to the callers, which requires only a single
cleaning operation for the entire AP switch.

The use of the page->private field affected the VM system of the host in
a bad way, and it's much much cleaner to simply use get_page(...) and
put_page(...) the right number of times.

Additionally, when switching host vectors, the new page was not always
fetched causing an early release of pages. This could both cause bugs
and produce some of the bad_page warnings.

The guest page table uses the guest mappings for all normal memory
mappings, and uses standard non-cache memory for device memory. But
still it's required to clean the D-cache when reading guest page table
entries.

Should be an optimization of the most common clean and invalidation
functions, but it doesn't have much effect. But maybe it depends on the
content of the caches.

Refactored a lot of the debugging/tracing code from arm.c to separate
trace.c file in arch/arm/kvm/...

Also introduced a simple array of events which are counted and printed
in a sorted maner to be able to tell where the time is spent. This could
be easily expanded to read a cycle counter and give more accurate
metrics.

Additionally, much of this should actually be done using the kernel perf
tool and tracepoints. However, the way that the rest of KVM does it
relies on newer kernel features than 2.6.29, and serial console on the
development devices does not yet work with anything newer, so we do this
quick and dirty for now. Before upstream, this should be improved.

If you invalidate dirty caches without cleaning them, you loose data,
which can result in host kernel NULL pointer dereferencing and all sorts
of fun.

The bitmask for the Rd and Rn fields in the MCRR instruction emulation
code was xor'ed instead of and'ed.