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Added 4-port register file and test logic.

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1 parent 801c744 commit 3fb3755d42c9dcf72e1797d4fc9cc8bfd9486c60 Vijay Nayar committed May 13, 2012
Showing with 74 additions and 0 deletions.
  1. +30 −0 src/reg_file.v
  2. +44 −0 test/test_reg_file.v
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30 src/reg_file.v
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+/**
+ * Register File.
+ * A small memory, typically built with flip-flops, that is very fast
+ * and is highly parallel. It is typically built with a small SRAM or
+ * Flip-Flops.
+ */
+module reg_file
+ // Set to 1 to make register $0 always read as 0.
+ #(parameter ZERO_REG = 0)
+ (
+ input clk,
+ input we1, we2,
+ input [3:0] a1, a2, wa1, wa2,
+ input [31:0] wd1, wd2,
+ output [31:0] rd1, rd2);
+
+ // Internal register memory
+ reg [31:0] rf[3:0];
+
+ // Two read-ports are combinational logic.
+ assign rd1 = (ZERO_REG && a1 != 0) ? rf[a1] : 0;
+ assign rd2 = (ZERO_REG && a2 != 0) ? rf[a2] : 0;
+
+ // Sequential write logic
+ always @(posedge clk) begin
+ if (we1) rf[wa1] <= wd1;
+ if (we2) rf[wa2] <= wd2;
+ end
+endmodule // reg_file
+
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44 test/test_reg_file.v
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+/**
+ * Test - Register File.
+ * Assure simultaneous reads and write are supported.
+ */
+module test_reg_file();
+
+ reg clk;
+ reg we1, we2;
+ reg [3:0] a1, a2, wa1, wa2;
+ reg [31:0] wd1, wd2;
+ wire [31:0] rd1, rd2;
+
+ // Instantiate the device-under-test (dut).
+ reg_file#(1) dut(clk, we1, we2, a1, a2, wa1, wa2, wd1, wd2, rd1, rd2);
+
+ // generate clock
+ always begin
+ clk = 1; #5;
+ clk = 0; #5;
+ end
+
+ // Apply test inputs one at a time and verify outputs.
+ initial begin
+ // Initialize a circular buffer.
+ $display("Starting Test.");
+
+ // Write into registers 1 and 2.
+ we1 = 1; we2 = 1; a1 = 0; a2 = 0; wa1 = 1; wa2 = 2; wd1 = 10; wd2 = 20; #11;
+
+ // Read registers 1 and 2.
+ we1 = 0; we2 = 0; a1 = 1; a2 = 2; #10;
+ if (rd1 !== 10 || rd2 !== 20)
+ $display("Read failed: rd1=%h, rd2=%h.", rd1, rd2);
+
+ // Check the zero-register.
+ a1 = 0; a2 = 0; #10;
+ if (rd1 !== 0 || rd2 !== 0)
+ $display("Read $0 failed: rd1=%h, rd2=%h.", rd1, rd2);
+
+ $display("Test Complete.");
+
+ end // initial begin
+endmodule // test_reg_file
+

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