From 9c5c2dd04d7339b26507ed88a88bd0ae81004cce Mon Sep 17 00:00:00 2001 From: Cameron Nemo Date: Fri, 23 Jul 2021 17:16:49 -0700 Subject: [PATCH 1/2] atf-rk3399-bl31: update to 2.5, add suspend patch --- srcpkgs/atf-rk3399-bl31/patches/suspend.patch | 172 ++++++++++++++++++ srcpkgs/atf-rk3399-bl31/template | 4 +- 2 files changed, 174 insertions(+), 2 deletions(-) create mode 100644 srcpkgs/atf-rk3399-bl31/patches/suspend.patch diff --git a/srcpkgs/atf-rk3399-bl31/patches/suspend.patch b/srcpkgs/atf-rk3399-bl31/patches/suspend.patch new file mode 100644 index 00000000000000..2c596ea4498f5c --- /dev/null +++ b/srcpkgs/atf-rk3399-bl31/patches/suspend.patch @@ -0,0 +1,172 @@ +From 9b672ea967dc8c88683654aee8866d2f9177c6c2 Mon Sep 17 00:00:00 2001 +From: Jimmy Brisson +Date: Mon, 29 Jun 2020 12:21:23 -0500 +Subject: [PATCH] fix(rk3399/suspend): correct LPDDR4 resume sequence + +This change adds 208 bytes to PMUSRAM, pushing the end of text from +0xff3b0de0 to 0xff3b0eb0, which is still shy of the maximum +0xff3b1000. + +Further, this skips enabling the watchdog when it's not being used +elsewhere, as you can't turn the watchdog off. + +Change-Id: I2e6fa3c7e01f2be6b32ce04ce479edf64e278554 +Signed-off-by: Jimmy Brisson +--- + +diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.c b/plat/rockchip/rk3399/drivers/dram/suspend.c +index 7f9fad1..a8b1c32 100644 +--- a/plat/rockchip/rk3399/drivers/dram/suspend.c ++++ b/plat/rockchip/rk3399/drivers/dram/suspend.c +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. ++ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -49,6 +49,7 @@ + + __pmusramdata uint32_t dpll_data[PLL_CON_COUNT]; + __pmusramdata uint32_t cru_clksel_con6; ++__pmusramdata uint8_t pmu_enable_watchdog0; + + /* + * Copy @num registers from @src to @dst +@@ -562,8 +563,14 @@ + + /* LPDDR4 f2 cann't do training, all training will fail */ + for (ch = 0; ch < ch_count; ch++) { +- mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, +- fn << 8); ++ /* ++ * Without this disabled for LPDDR4 we end up writing 0's ++ * in place of real data in an interesting pattern. ++ */ ++ if (sdram_params->dramtype != LPDDR4) { ++ mmio_clrsetbits_32(PHY_REG(ch, 896), (0x3 << 8) | 1, ++ fn << 8); ++ } + + /* data_training failed */ + if (data_training(ch, sdram_params, PI_FULL_TRAINING)) +@@ -748,13 +755,44 @@ + phy_regs->phy896[0] &= ~(0x3 << 8); + } + ++__pmusramfunc void phy_dll_bypass_set(uint32_t ch, uint32_t freq) ++{ ++ if (freq <= (125 * 1000 * 1000)) { ++ /* Set master mode to SW for slices*/ ++ mmio_setbits_32(PHY_REG(ch, 86), 3 << 10); ++ mmio_setbits_32(PHY_REG(ch, 214), 3 << 10); ++ mmio_setbits_32(PHY_REG(ch, 342), 3 << 10); ++ mmio_setbits_32(PHY_REG(ch, 470), 3 << 10); ++ /* Set master mode to SW for address slices*/ ++ mmio_setbits_32(PHY_REG(ch, 547), 3 << 18); ++ mmio_setbits_32(PHY_REG(ch, 675), 3 << 18); ++ mmio_setbits_32(PHY_REG(ch, 803), 3 << 18); ++ } else { ++ /* Clear SW master mode for slices*/ ++ mmio_clrbits_32(PHY_REG(ch, 86), 3 << 10); ++ mmio_clrbits_32(PHY_REG(ch, 214), 3 << 10); ++ mmio_clrbits_32(PHY_REG(ch, 342), 3 << 10); ++ mmio_clrbits_32(PHY_REG(ch, 470), 3 << 10); ++ /* Clear SW master mode for address slices*/ ++ mmio_clrbits_32(PHY_REG(ch, 547), 3 << 18); ++ mmio_clrbits_32(PHY_REG(ch, 675), 3 << 18); ++ mmio_clrbits_32(PHY_REG(ch, 803), 3 << 18); ++ } ++} ++ + __pmusramfunc void dmc_resume(void) + { + struct rk3399_sdram_params *sdram_params = &sdram_config; + uint32_t channel_mask = 0; + uint32_t channel; + +- pmusram_enable_watchdog(); ++ /* ++ * We can't turn off the watchdog, so if we have not turned it on before ++ * we should not turn it on here. ++ */ ++ if ((pmu_enable_watchdog0 & 0x1) == 0x1) { ++ pmusram_enable_watchdog(); ++ } + pmu_sgrf_rst_hld_release(); + restore_pmu_rsthold(); + sram_secure_timer_init(); +@@ -772,6 +810,13 @@ + retry: + for (channel = 0; channel < sdram_params->num_channels; channel++) { + phy_pctrl_reset(channel); ++ /* ++ * Without this, LPDDR4 will write 0's in place of real data ++ * in a strange pattern. ++ */ ++ if (sdram_params->dramtype == LPDDR4) { ++ phy_dll_bypass_set(channel, sdram_params->ddr_freq); ++ } + pctl_cfg(channel, sdram_params); + } + +@@ -788,8 +833,12 @@ + if (sdram_params->dramtype == LPDDR3) + sram_udelay(10); + +- /* If traning fail, retry to do it again. */ +- if (data_training(channel, sdram_params, PI_FULL_TRAINING)) ++ /* ++ * Training here will always fail for LPDDR4, so skip it ++ * If traning fail, retry to do it again. ++ */ ++ if (sdram_params->dramtype != LPDDR4 && ++ data_training(channel, sdram_params, PI_FULL_TRAINING)) + goto retry; + + set_ddrconfig(sdram_params, channel, +diff --git a/plat/rockchip/rk3399/drivers/dram/suspend.h b/plat/rockchip/rk3399/drivers/dram/suspend.h +index b99a926..1389944 100644 +--- a/plat/rockchip/rk3399/drivers/dram/suspend.h ++++ b/plat/rockchip/rk3399/drivers/dram/suspend.h +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved. ++ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -7,6 +7,7 @@ + #ifndef SUSPEND_H + #define SUSPEND_H + ++#include + #include + + #define KHz (1000) +@@ -22,5 +23,6 @@ + + void dmc_suspend(void); + __pmusramfunc void dmc_resume(void); ++extern __pmusramdata uint8_t pmu_enable_watchdog0; + + #endif /* SUSPEND_H */ +diff --git a/plat/rockchip/rk3399/drivers/pmu/pmu.c b/plat/rockchip/rk3399/drivers/pmu/pmu.c +index faee678..3084c4f 100644 +--- a/plat/rockchip/rk3399/drivers/pmu/pmu.c ++++ b/plat/rockchip/rk3399/drivers/pmu/pmu.c +@@ -1,5 +1,5 @@ + /* +- * Copyright (c) 2016-2019, ARM Limited and Contributors. All rights reserved. ++ * Copyright (c) 2016-2021, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ +@@ -1324,6 +1324,7 @@ + store_wdt0[i] = mmio_read_32(WDT0_BASE + i * 4); + store_wdt1[i] = mmio_read_32(WDT1_BASE + i * 4); + } ++ pmu_enable_watchdog0 = (uint8_t) store_wdt0[0] & 0x1; + } + + void wdt_register_restore(void) diff --git a/srcpkgs/atf-rk3399-bl31/template b/srcpkgs/atf-rk3399-bl31/template index 9eb9330fbae10f..1a47315f89bd62 100644 --- a/srcpkgs/atf-rk3399-bl31/template +++ b/srcpkgs/atf-rk3399-bl31/template @@ -1,6 +1,6 @@ # Template file for 'atf-rk3399-bl31' pkgname=atf-rk3399-bl31 -version=2.4 +version=2.5 revision=1 archs="aarch64*" wrksrc="trusted-firmware-a-${version}" @@ -10,7 +10,7 @@ maintainer="Cameron Nemo " license="BSD-3-Clause" homepage="https://developer.trustedfirmware.org/dashboard/view/6/" distfiles="https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/snapshot/trusted-firmware-a-${version}.tar.gz" -checksum=bf3eb3617a74cddd7fb0e0eacbfe38c3258ee07d4c8ed730deef7a175cc3d55b +checksum=ad8a2ffcbcd12d919723da07630fc0840c3c2fba7656d1462e45488e42995d7c nostrip=yes do_build() { From b5e39982677173b2452b9d7b68efc5adf303d515 Mon Sep 17 00:00:00 2001 From: Cameron Nemo Date: Fri, 23 Jul 2021 17:17:14 -0700 Subject: [PATCH 2/2] pinebookpro-uboot: update to 2021.07 --- ...x-hang-when-multiple-controllers-exit.diff | 69 +++++++++++++++++++ srcpkgs/pinebookpro-uboot/template | 4 +- 2 files changed, 71 insertions(+), 2 deletions(-) create mode 100644 srcpkgs/pinebookpro-uboot/patches/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.diff diff --git a/srcpkgs/pinebookpro-uboot/patches/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.diff b/srcpkgs/pinebookpro-uboot/patches/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.diff new file mode 100644 index 00000000000000..bd912ffc6dc6d9 --- /dev/null +++ b/srcpkgs/pinebookpro-uboot/patches/phy-rockchip-inno-usb2-fix-hang-when-multiple-controllers-exit.diff @@ -0,0 +1,69 @@ +Source: https://patchwork.ozlabs.org/project/uboot/patch/20210406151059.1187379-1-icenowy@aosc.io/ + +diff --git a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +index 62b8ba3a4a..be9cc99d90 100644 +--- a/drivers/phy/rockchip/phy-rockchip-inno-usb2.c ++++ b/drivers/phy/rockchip/phy-rockchip-inno-usb2.c +@@ -62,6 +62,8 @@ struct rockchip_usb2phy { + void *reg_base; + struct clk phyclk; + const struct rockchip_usb2phy_cfg *phy_cfg; ++ int init_count; ++ int power_on_count; + }; + + static inline int property_enable(void *reg_base, +@@ -92,6 +94,10 @@ static int rockchip_usb2phy_power_on(struct phy *phy) + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + ++ priv->power_on_count++; ++ if (priv->power_on_count != 1) ++ return 0; ++ + property_enable(priv->reg_base, &port_cfg->phy_sus, false); + + /* waiting for the utmi_clk to become stable */ +@@ -106,6 +112,10 @@ static int rockchip_usb2phy_power_off(struct phy *phy) + struct rockchip_usb2phy *priv = dev_get_priv(parent); + const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + ++ priv->power_on_count--; ++ if (priv->power_on_count != 0) ++ return 0; ++ + property_enable(priv->reg_base, &port_cfg->phy_sus, true); + + return 0; +@@ -118,6 +128,10 @@ static int rockchip_usb2phy_init(struct phy *phy) + const struct rockchip_usb2phy_port_cfg *port_cfg = us2phy_get_port(phy); + int ret; + ++ priv->init_count++; ++ if (priv->init_count != 1) ++ return 0; ++ + ret = clk_enable(&priv->phyclk); + if (ret) { + dev_err(phy->dev, "failed to enable phyclk (ret=%d)\n", ret); +@@ -140,6 +154,10 @@ static int rockchip_usb2phy_exit(struct phy *phy) + struct udevice *parent = dev_get_parent(phy->dev); + struct rockchip_usb2phy *priv = dev_get_priv(parent); + ++ priv->init_count--; ++ if (priv->init_count != 0) ++ return 0; ++ + clk_disable(&priv->phyclk); + + return 0; +@@ -212,6 +230,9 @@ static int rockchip_usb2phy_probe(struct udevice *dev) + return ret; + } + ++ priv->power_on_count = 0; ++ priv->init_count = 0; ++ + return 0; + } + diff --git a/srcpkgs/pinebookpro-uboot/template b/srcpkgs/pinebookpro-uboot/template index db629c4a8e53d8..3b67c6036973dd 100644 --- a/srcpkgs/pinebookpro-uboot/template +++ b/srcpkgs/pinebookpro-uboot/template @@ -1,7 +1,7 @@ # Template file for 'pinebookpro-uboot' pkgname=pinebookpro-uboot reverts="20200212_1 20200212_2" -version=2020.10 +version=2021.07 revision=1 archs="aarch64*" wrksrc="u-boot-${version}" @@ -13,7 +13,7 @@ maintainer="Renato Aguiar " license="GPL-2.0-only, BSD-3-Clause" homepage="https://www.denx.de/wiki/U-Boot/" distfiles="https://ftp.denx.de/pub/u-boot/u-boot-${version}.tar.bz2" -checksum=0d481bbdc05c0ee74908ec2f56a6daa53166cc6a78a0e4fac2ac5d025770a622 +checksum=312b7eeae44581d1362c3a3f02c28d806647756c82ba8c72241c7cdbe68ba77e do_configure() { unset CFLAGS CXXFLAGS CPPFLAGS LDFLAGS