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Commits on Feb 7, 2015
  1. Bundle pre-built CY7C68013A firmware.

    vpelletier committed Feb 7, 2015
    Update installation instructions.
  2. device: Handle EP0 data state in a busy loop.

    vpelletier committed Feb 7, 2015
    Doubles processing speed compared to using an IRQ (0.22s to process the
    whole configuration stream, 0.40 with IRQ), and firmware has nothing else
    to do at that point.
  3. device: Put FPGA in reset on suspend.

    vpelletier committed Feb 7, 2015
    Otherwise, its state on resume is invalid - and configuration stream is
    sent on each capture session anyway.
Commits on Feb 6, 2015
  1. device: Adapt EP2FIFOPF level depending on bandwidth.

    vpelletier committed Feb 6, 2015
    Keep low latency on low bandwidth and low packet frequency on high
    bandwidth.
  2. fw: Coding style.

    vpelletier committed Feb 1, 2015
  3. device: Add (disabled) memory access commands.

    vpelletier committed Jan 31, 2015
    Invaluable for debugging.
  4. CY7C68013A: Implement a standard-compliant configuration.

    vpelletier committed Feb 6, 2015
    Commands which used to go through USB2-incompatible EP1 are now vendor
    commands.
    Add support for it in capture, without dropping compatibility with
    original firmware.
Commits on Feb 5, 2015
  1. device: Use default storage type instead of __idata.

    vpelletier committed Feb 4, 2015
    __idata was likely used instead of __data here, as it does not make much
    sense. Also, as __data is the default, just leave it out.
Commits on Feb 4, 2015
  1. capture: Make signal handling payload synchronous.

    vpelletier committed Feb 4, 2015
    Should solve race conditions where sending SIGINT would (optionally) print
    "Exiting..." but process would be stuck somewhere in libusb.
Commits on Feb 3, 2015
Commits on Feb 2, 2015
  1. display: Use non-blocking IO.

    vpelletier committed Feb 2, 2015
    Reduces buffer-induced latency in one more place.
  2. CY7C68013A: Enable peep optimisations.

    vpelletier committed Feb 2, 2015
    Also, enable verbose asm generation, to track peep changes.
Commits on Feb 1, 2015
  1. CY7C68013A: Add reload-cycfx2prog make target.

    vpelletier committed Feb 1, 2015
    To reprogram FX2 without having to re-plug it.
  2. capture: Empty EP2 before programming FPGA.

    vpelletier committed Feb 1, 2015
    Trailing capture data may be present in FX2 buffers (already committed to
    USB, so there seem to be no way of discarding it on EP2 - unlike setting
    EP1 BUSY bit). FX2 EP2 buffer can be up to 4*512B, so read 2048 and expect
    at most the second read to timeout.
  3. capture: Discard data once stop condition reached.

    vpelletier committed Feb 1, 2015
    Reduces capture file size by a few kB.
  4. device: Move FIFORESET from config stop to config start.

    vpelletier committed Feb 1, 2015
    There is no guarantee on stop that FPGA isn't already pushing data, so
    discard FIFO content when it is in configuration mode.
Commits on Jan 31, 2015
  1. capture: Make output unbuffered.

    vpelletier committed Jan 31, 2015
    Buffering flushes on newline, and we are emitting binary.
  2. device: Add IN-Bulk-NAK interrupt handler.

    vpelletier committed Jan 31, 2015
    Makes the FX2 push any available data to host, reducing buffer lag in
    low-bandwidth conditions.