Skip to content

HTTPS clone URL

Subversion checkout URL

You can clone with HTTPS or Subversion.

Download ZIP
Browse files

main: Wired up PIO 13 and DC 8.3.

  • Loading branch information...
commit 2a2d79ea84b6d06d6198d56af393acc7cfdbe3ca 1 parent 362e064
@waldheinz authored
Showing with 101 additions and 40 deletions.
  1. +38 −38 MPC4.xise
  2. +63 −2 Main.vhd
View
76 MPC4.xise
@@ -16,51 +16,51 @@
<files>
<file xil_pn:name="Main.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="pins.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="DS8205D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="t80/T80.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="t80/T80_ALU.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="t80/T80_MCode.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="t80/T80_Reg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="t80/T80_Pack.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="UA880D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="t80/T80a.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="U2732.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="RESET_LOGIC.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="tb_reset_logic.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -69,11 +69,11 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="ipcore_dir/CLOCK_GEN.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="tb_main.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="17"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
@@ -123,23 +123,23 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="UA858D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="UA857D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="RAM_256.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="UA855D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
- <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+ <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="tb_UA855D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="113"/>
@@ -390,8 +390,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_UA855D" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_UA855D" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_main" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_main" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -409,7 +409,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_UA855D" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_main" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -459,7 +459,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb_UA855D|behavior" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb_main|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="MPC4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
View
65 Main.vhd
@@ -47,6 +47,7 @@ architecture RTL of Main is
signal cpu16_bus_ack : std_logic;
signal aus_n : std_logic;
signal clock_locked : std_logic; -- locked output of the 4MHz DCG
+ signal bank_n : std_logic_vector(7 downto 0); -- RAM bank select
-- DMA signals
signal dma17_int_n : std_logic;
@@ -59,6 +60,10 @@ architecture RTL of Main is
signal ctc_zcto : std_logic_vector(2 downto 0);
signal ctc_21_1_int_n: std_logic;
+ -- PIO 13 signals
+ signal pio_13_int_n : std_logic;
+ signal pio_13_port_a : std_logic_vector(7 downto 0);
+
COMPONENT CLOCK_GEN
PORT(
CLK_IN1 : IN std_logic;
@@ -177,6 +182,28 @@ architecture RTL of Main is
);
END COMPONENT;
+ COMPONENT UA855D
+ PORT(
+ CLK : IN std_logic;
+ B_A_SEL : IN std_logic;
+ C_D_SEL : IN std_logic;
+ CS_n : IN std_logic;
+ M1_n : IN std_logic;
+ IORQ_n : IN std_logic;
+ RD_n : IN std_logic;
+ IEI : IN std_logic;
+ ASTB_n : IN std_logic;
+ BSTB_n : IN std_logic;
+ D : INOUT std_logic_vector(7 downto 0);
+ A : INOUT std_logic_vector(7 downto 0);
+ B : INOUT std_logic_vector(7 downto 0);
+ IEO : OUT std_logic;
+ INT_n : OUT std_logic;
+ ARDY : OUT std_logic;
+ BRDY : OUT std_logic
+ );
+ END COMPONENT;
+
begin
process (SW, aus_n, reset_n)
begin
@@ -218,7 +245,7 @@ begin
RAM : RAM_256 PORT MAP(
RD_n => rd,
- BANK_n => (others => '0'),
+ BANK_n => bank_n,
COM_n => com_n,
A => addr_bus(16 downto 1),
RFSH_n => rfsh_n,
@@ -247,7 +274,9 @@ begin
INT_n => dma17_int_n
);
- int_n <= dma17_int_n and ctc_21_1_int_n;
+ -- determine value of wired-or interrupt signal
+ int_n <= dma17_int_n and ctc_21_1_int_n and pio_13_int_n;
+
nmi_n <= '1';
busrq_n <= '1';
@@ -317,4 +346,36 @@ begin
chip_select(4 downto 1) <= dc_8_4_out(3 downto 0);
chip_select(8 downto 6) <= dc_8_4_out(7 downto 5);
+
+ PIO_13 : UA855D PORT MAP(
+ CLK => clock_n,
+ D => data_bus,
+ B_A_SEL => addr_bus(1),
+ C_D_SEL => addr_bus(2),
+ CS_n => chip_select(4),
+ M1_n => m1,
+ IORQ_n => iorq_n,
+ RD_n => rd,
+ IEI => '1', -- really SIO 18.2 IEO
+-- IEO => ,
+ INT_n => pio_13_int_n,
+ A => pio_13_port_a,
+ -- ARDY => ,
+ ASTB_n => '1', -- really unconnected
+ -- B => , )
+ -- BRDY => , ) to connector 5.2
+ BSTB_n => '1' -- )
+ );
+
+ DC_8_3: DS8205D PORT MAP(
+ A(0) => pio_13_port_a(4),
+ A(1) => pio_13_port_a(5),
+ A(2) => pio_13_port_a(3),
+ E1_n => db_10,
+ E2_n => db_10,
+ E3 => pio_13_port_a(6),
+ O(3 downto 0) => bank_n(7 downto 4),
+ O(7 downto 4) => bank_n(3 downto 0)
+ );
+
end RTL;
Please sign in to comment.
Something went wrong with that request. Please try again.