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PIO: Can set port modes.

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1 parent df4c074 commit 362e06441a8c9f1c688f483be29ac49d2ab0d6fb @waldheinz committed Apr 13, 2012
Showing with 65 additions and 41 deletions.
  1. +22 −22 MPC4.xise
  2. +31 −6 UA855D.vhd
  3. +12 −13 tb_UA855D.vhd
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44 MPC4.xise
@@ -16,50 +16,50 @@
<files>
<file xil_pn:name="Main.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="15"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="15"/>
</file>
<file xil_pn:name="pins.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="DS8205D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="7"/>
</file>
<file xil_pn:name="t80/T80.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="t80/T80_ALU.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="t80/T80_MCode.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="t80/T80_Reg.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="t80/T80_Pack.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file>
<file xil_pn:name="UA880D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="8"/>
</file>
<file xil_pn:name="t80/T80a.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="6"/>
</file>
<file xil_pn:name="U2732.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="11"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="11"/>
</file>
<file xil_pn:name="RESET_LOGIC.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="12"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="12"/>
</file>
<file xil_pn:name="tb_reset_logic.vhd" xil_pn:type="FILE_VHDL">
@@ -69,11 +69,11 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="78"/>
</file>
<file xil_pn:name="ipcore_dir/CLOCK_GEN.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="14"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="14"/>
</file>
<file xil_pn:name="tb_main.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="16"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
@@ -123,23 +123,23 @@
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="90"/>
</file>
<file xil_pn:name="UA858D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="9"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="9"/>
</file>
<file xil_pn:name="UA857D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="10"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="10"/>
</file>
<file xil_pn:name="RAM_256.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="13"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="13"/>
</file>
<file xil_pn:name="UA855D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="tb_UA855D.vhd" xil_pn:type="FILE_VHDL">
- <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+ <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="113"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="113"/>
@@ -390,8 +390,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
- <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_main" xil_pn:valueState="non-default"/>
- <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_main" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/tb_UA855D" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.tb_UA855D" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -409,7 +409,7 @@
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
- <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_main" xil_pn:valueState="default"/>
+ <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.tb_UA855D" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -459,7 +459,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
- <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb_main|behavior" xil_pn:valueState="non-default"/>
+ <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|tb_UA855D|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="MPC4" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
View
37 UA855D.vhd
@@ -1,15 +1,12 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---use IEEE.NUMERIC_STD.ALL;
+use IEEE.NUMERIC_STD.ALL;
entity UA855D is
Port (
-- Clock
- C : in STD_LOGIC;
+ CLK : in STD_LOGIC;
-- CPU Data Bus
D : inout STD_LOGIC_VECTOR (7 downto 0);
@@ -39,9 +36,37 @@ entity UA855D is
end UA855D;
architecture RTL of UA855D is
- signal reset_n : std_logic;
+
+ type PORT_MODE_TYPE is (M_OUTP, M_INPU, M_BIDI, M_CTRL);
+ type PORT_MODE_TABLE is array(1 downto 0) of PORT_MODE_TYPE;
+
+ signal port_mode : PORT_MODE_TABLE;
+
+ signal reset_n : std_logic; -- internal async reset signal
+ signal port_select : integer range 0 to 1; -- 0 is port A, 1 is B
+
begin
+ D <= (others => 'Z');
reset_n <= '0' when (M1_n = '0' and RD_n = '1' and IORQ_n = '1') else '1';
+ port_select <= 0 when B_A_SEL = '0' else 1;
+
+ proc_ctrl : process (B_A_SEL, C_D_SEL, CLK, D, RD_n, port_select)
+ begin
+ if (rising_edge(CLK) and RD_n = '1' and C_D_SEL = '1') then
+ case D(3 downto 0) is
+ when "1111" => -- set mode
+ case D(7 downto 6) is
+ when "00" => port_mode(port_select) <= M_OUTP;
+ when "01" => port_mode(port_select) <= M_INPU;
+ when "10" => port_mode(port_select) <= M_BIDI;
+ when others => port_mode(port_select) <= M_CTRL;
+ end case;
+
+ when others => null;
+
+ end case;
+ end if;
+ end process;
end RTL;
View
25 tb_UA855D.vhd
@@ -15,7 +15,7 @@ ARCHITECTURE behavior OF tb_UA855D IS
COMPONENT UA855D
PORT(
- C : IN std_logic;
+ CLK : IN std_logic;
D : INOUT std_logic_vector(7 downto 0);
B_A_SEL : IN std_logic;
C_D_SEL : IN std_logic;
@@ -65,7 +65,7 @@ BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: UA855D PORT MAP (
- C => C,
+ CLK => C,
D => D,
B_A_SEL => B_A_SEL,
C_D_SEL => C_D_SEL,
@@ -92,24 +92,23 @@ BEGIN
C <= '1';
wait for C_period/2;
end process;
-
-
- -- Stimulus process
+
stim_proc: process
- begin
- -- hold reset state for 100 ns.
- wait for 100 ns;
-
- M1_n <= '0';
+ begin
RD_n <= '1';
IORQ_n <= '1';
wait for C_period*10;
+ CS_n <= '1';
M1_n <= '1';
-
- -- insert stimulus here
-
+ D <= "11001111";
+
+ wait for 10 ns;
+
+ CS_n <= '0';
+ C_D_SEL <= '1';
+
wait;
end process;

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