From 5f0163b2df62f400aebd032c4651256e678db042 Mon Sep 17 00:00:00 2001 From: Richard Hu Date: Tue, 18 Apr 2017 17:48:13 +0800 Subject: [PATCH] wandboard: add DDR initialization for imx6qp --- board/wandboard/spl.c | 146 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 3 deletions(-) diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 902003710d..8a23110e63 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -32,6 +32,7 @@ DECLARE_GLOBAL_DATA_PTR; #define IMX6DQ_DRIVE_STRENGTH 0x30 #define IMX6SDL_DRIVE_STRENGTH 0x28 +#define IMX6QP_DRIVE_STRENGTH 0x28 /* configure MX6Q/DUAL mmdc DDR io registers */ static struct mx6dq_iomux_ddr_regs mx6dq_ddr_ioregs = { @@ -266,14 +267,153 @@ static void gpr_init(void) /* enable AXI cache for VDOA/VPU/IPU */ writel(0xF00000CF, &iomux->gpr[4]); + /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ - writel(0x007F007F, &iomux->gpr[6]); - writel(0x007F007F, &iomux->gpr[7]); + if (is_mx6dqp()) { + writel(0x77177717, &iomux->gpr[6]); + writel(0x77177717, &iomux->gpr[7]); + } else { + writel(0x007F007F, &iomux->gpr[6]); + writel(0x007F007F, &iomux->gpr[7]); + } +} + +static void spl_dram_init_imx6qp_lpddr3(void) +{ + /* i.MX6QP */ + /* DDR IO TYPE */ + writel(0x000C0000, IOMUXC_BASE_ADDR + 0x798); + writel(0x00000000, IOMUXC_BASE_ADDR + 0x758); + /* Clock */ + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x588); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x594); + /* Address */ + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x56c); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x578); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x74c); + /* Control */ + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x57c);//fix to apply for LPDDR2 + + writel(0x00000000, IOMUXC_BASE_ADDR + 0x58c); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x59c); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5a0); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x78c); + /* Data Strobe */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x750); + + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5a8); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b0); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x524); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x51c); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x518); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x50c); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b8); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5c0); + /* Data */ + writel(0x00020000, IOMUXC_BASE_ADDR + 0x774); + + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x784); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x788); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x794); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x79c); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a0); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a4); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x7a8); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x748); + + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5ac); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5b4); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x528); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x520); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x514); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x510); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5bc); + writel(IMX6QP_DRIVE_STRENGTH, IOMUXC_BASE_ADDR + 0x5c4); + + /* MMDC0_MDSCR + set the Configuration request bit during MMDC set up */ + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + + /* Calibrations */ + /* ZQ */ + writel(0xa1390003, MMDC_P0_BASE_ADDR + 0x800); + /* write leveling */ + writel(0x00060004, MMDC_P0_BASE_ADDR + 0x80c); + writel(0x000B0004, MMDC_P0_BASE_ADDR + 0x810); + writel(0x00000004, MMDC_P1_BASE_ADDR + 0x80c); + writel(0x00000000, MMDC_P1_BASE_ADDR + 0x810); + /* DQS gating, read delay, write delay calibration values + based on calibration compare of 0x00ffff00 */ + writel(0x03040314, MMDC_P0_BASE_ADDR + 0x83c); + writel(0x03080300, MMDC_P0_BASE_ADDR + 0x840); + writel(0x03000310, MMDC_P1_BASE_ADDR + 0x83c); + writel(0x0268023C, MMDC_P1_BASE_ADDR + 0x840); + + writel(0x4034363A, MMDC_P0_BASE_ADDR + 0x848); + writel(0x36302C3C, MMDC_P1_BASE_ADDR + 0x848); + + writel(0x3E3E4046, MMDC_P0_BASE_ADDR + 0x850); + writel(0x483A4844, MMDC_P1_BASE_ADDR + 0x850); + + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P0_BASE_ADDR + 0x828); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x81c); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x820); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x824); + writel(0x33333333, MMDC_P1_BASE_ADDR + 0x828); + + writel(0x24912489, MMDC_P0_BASE_ADDR + 0x8c0); + writel(0x24914452, MMDC_P1_BASE_ADDR + 0x8c0); + + writel(0x00000800, MMDC_P0_BASE_ADDR + 0x8b8); + writel(0x00000800, MMDC_P1_BASE_ADDR + 0x8b8); + /* MMDC init: + in DDR3, 64-bit mode, only MMDC0 is initiated: */ + writel(0x00020036, MMDC_P0_BASE_ADDR + 0x004); + writel(0x09444040, MMDC_P0_BASE_ADDR + 0x008); + writel(0x898E79A4, MMDC_P0_BASE_ADDR + 0x00c); + writel(0xDB538F64, MMDC_P0_BASE_ADDR + 0x010); + writel(0x01FF00DD, MMDC_P0_BASE_ADDR + 0x014); + + writel(0x00011740, MMDC_P0_BASE_ADDR + 0x018); + writel(0x00008000, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x000026D2, MMDC_P0_BASE_ADDR + 0x02c); + writel(0x008E1023, MMDC_P0_BASE_ADDR + 0x030); + writel(0x00000047, MMDC_P0_BASE_ADDR + 0x040); + + writel(0x14420000, MMDC_P0_BASE_ADDR + 0x400); + writel(0x841A0000, MMDC_P0_BASE_ADDR + 0x000); + writel(0x00400c58, MMDC_P0_BASE_ADDR + 0x890); + + /* add noc DDR configuration */ + writel(0x00000000, NOC_DDR_BASE_ADDR + 0x008); + writel(0x2871C39B, NOC_DDR_BASE_ADDR + 0x00c); + writel(0x000005B4, NOC_DDR_BASE_ADDR + 0x038); + writel(0x00000040, NOC_DDR_BASE_ADDR + 0x014); + writel(0x00000020, NOC_DDR_BASE_ADDR + 0x028); + writel(0x00000020, NOC_DDR_BASE_ADDR + 0x02c); + + writel(0x02088032, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00008033, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x00048031, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x19308030, MMDC_P0_BASE_ADDR + 0x01c); + writel(0x04008040, MMDC_P0_BASE_ADDR + 0x01c); + + writel(0x00007800, MMDC_P0_BASE_ADDR + 0x020); + writel(0x00022227, MMDC_P0_BASE_ADDR + 0x818); + writel(0x00022227, MMDC_P1_BASE_ADDR + 0x818); + writel(0x00025576, MMDC_P0_BASE_ADDR + 0x004); + writel(0x00011006, MMDC_P0_BASE_ADDR + 0x404); + writel(0x00000000, MMDC_P0_BASE_ADDR + 0x01c); } static void spl_dram_init(void) { - if (is_cpu_type(MXC_CPU_MX6SOLO)) { + if (is_mx6dqp()) { + spl_dram_init_imx6qp_lpddr3(); + } else if (is_cpu_type(MXC_CPU_MX6SOLO)) { mx6sdl_dram_iocfg(32, &mx6sdl_ddr_ioregs, &mx6sdl_grp_ioregs); mx6_dram_cfg(&mem_s, &mx6s_512m_mmdc_calib, &h5tq2g63dfr); } else if (is_cpu_type(MXC_CPU_MX6DL)) {