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Commits on Apr 24, 2017
  1. wandboard: display board revision information after PMIC initialization

    richard-hu committed Apr 24, 2017
    The way to tell the difference between wandboard rev.B1/C1 and rev.D1 is to detect if
    there is PMIC on I2C bus 3.
Commits on Apr 18, 2017
  1. wandboard: add wandboard rev.D1 support

    richard-hu committed Jan 23, 2017
    wandboard rev.D1 adds PMIC and replaces ethernet phy AR8031 with AR8035.
    Upgrade WIFI/BT chip to BCM4339/BCM43430 from BCM4329/BCM4330.
  2. wandboard: unify revision detection mechanism with u-boot fslc

    richard-hu committed Jan 23, 2017
    Merge with Fabio's work on u-boot 2016.11+fslc
  3. wandboard: separate the wnadboard dts files to c1 and b1 revision.

    wigcheng authored and richard-hu committed Mar 24, 2016
    implement using check pin.
  4. wandboard: Add environment to switch on/off auto-detecting of display

    richard-hu committed Jul 3, 2015
    e.g. For 7-inch LVDS display:
    setenv display_autodetect off
    setenv displayinfo 'video=mxcfb0:dev=ldb,1024x600@60,if=RGB24,bpp=32'
  5. wandboard: Switch to SPL support

    Fabio Estevam authored and richard-hu committed May 11, 2015
    Currently we need to build one U-boot image for each of the wandboard
    variants: quad, dual-lite and solo.
    
    By switching to SPL we can support all these variants with a single binary,
    which is very convenient.
    
    Based on the work from Richard Hu.
    
    Tested kernel booting on the three boards.
    
    Signed-off-by: Richard Hu <hakahu@gmail.com>
    Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
    Tested-by: Vagrant Cascadian <vagrant@aikidev.net>
    Reviewed-by: Stefano Babic <sbabic@denx.de>
    
    Conflicts:
    
    	configs/wandboard_dl_defconfig
    	configs/wandboard_quad_defconfig
    	configs/wandboard_solo_defconfig
Commits on Jun 6, 2016
  1. MLK-12883 usb: limit USB_MAX_XFER_BLK to 256

    MrVan committed Jun 6, 2016
    For Some USB mass storage devices, such as:
    "
     - Kingston DataTraveler 2.0 001D7D06CF09B04199C7B3EA
     - Class: (from Interface) Mass Storage
     - PacketSize: 64  Configurations: 1
     - Vendor: 0x0930  Product 0x6545 Version 1.16
    "
    When `usb read 0x80000000 0 0x2000`, we met
    "EHCI timed out on TD - token=0x80008d80".
    
    The devices does not support scsi VPD page, we are not able
    to get the maximum transfer length for READ(10)/WRITE(10).
    
    So we limit this to 256 blocks as READ(6).
    
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    (cherry picked from commit df0052575b2bc9d66ae73584768e1a457ed5d914)
  2. MLK-12884 mx7dsabresd: Fix LCD_PWR_EN output setting

    Ye Li
    Ye Li committed Jun 6, 2016
    LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
    D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
    is actually 1.2V.
    
    Signed-off-by: Ye Li <ye.li@nxp.com>
    (cherry picked from commit 28eb616b6c49de492cc0cdb3ad5b618bed77960f)
Commits on May 31, 2016
  1. MLK-12865 Nand: Fix BCH debug1 register access issue

    Ye Li
    Ye Li committed May 31, 2016
    Should have "&" to access the register address, otherwise uboot will hang.
    
    Signed-off-by: Ye Li <ye.li@nxp.com>
    (cherry picked from commit 806b2966f155b8ecef4182fca7151d07b1a9f420)
Commits on May 24, 2016
  1. imx: iomux-v3: fix UART input selects

    falstaff84 authored and nxpfrankli committed May 5, 2016
    Several UART input selects are missing. The fourth input select
    for UART2_TX_DATA_ALT0 is actually also missing in the documentation.
    (at least in Rev. B of the i.MX 7Dual Reference Manual). However,
    when looking at the tables of other input selects, it is very natural
    that there must be an input select for the UART2_TX_DATA_ALT0 pad.
    The Colibri iMX7 also uses that pad for UART2 RX (in DTE mode), and
    it was required to set that particular input select register to get a
    working UART2.
    
    From https://www.mail-archive.com/u-boot@lists.denx.de/msg211942.html
    
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    (cherry picked from commit ee6717667799d70a42f00ba46d96f3f34c78f497)
  2. MLK-12693-2 nand: mxs: correct bitflip for erased NAND page

    MrVan authored and nxpfrankli committed May 8, 2016
    This patch is a porting of
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=e4dacc44d22e9474ec456cb330df525cd805ea38
    "
    i.MX6QP and i.MX7D BCH module integrated a new feature to detect the
    bitflip number for erased NAND page. So for these two platform, set the
    erase threshold to gf/2 and if bitflip detected, GPMI driver will
    correct the data to all 0xFF.
    
    Also updated the imx6qp dts file to ditinguish the GPMI module for i.MX6Q
    with the one for i.MX6QP.
    "
    
    In this patch, i.MX6UL is added and threshold changed to use ecc_strength.
    
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    (cherry picked from commit 489929be0221bb7d4c46bb5bc6083650b78f73e0)
  3. MLK-12693-1 nand: mxs: fix the bitflips for erased page when uncorrec…

    MrVan authored and nxpfrankli committed May 6, 2016
    …table error
    
    This patch is porting from linux:
    http://git.freescale.com/git/cgit.cgi/imx/linux-2.6-imx.git/commit/?h=imx_4.1.15_1.0.0_ga&id=3d42fcece496224fde59f9343763fb2dfc5b0768
    
    "
    We may meet the bitflips in reading an erased page(contains all 0xFF),
    this may causes the UBIFS corrupt, please see the log from Elie:
    
    -----------------------------------------------------------------
    [    3.831323] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [    3.845026] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [    3.858710] UBI warning: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read only 16384 bytes, retry
    [    3.872408] UBI error: ubi_io_read: error -74 (ECC error) while reading 16384 bytes from PEB 443:245760, read 16384 bytes
    ...
    [    4.011529] UBIFS error (pid 36): ubifs_recover_leb: corrupt empty space LEB 27:237568, corruption starts at 9815
    [    4.021897] UBIFS error (pid 36): ubifs_scanned_corruption: corruption at LEB 27:247383
    [    4.030000] UBIFS error (pid 36): ubifs_scanned_corruption: first 6569 bytes from LEB 27:247383
    -----------------------------------------------------------------
    
    This patch does a check for the uncorrectable failure in the following steps:
    
       [0] set the threshold.
           The threshold is set based on the truth:
           "A single 0 bit will lead to gf_len(13 or 14) bits 0 after the BCH
            do the ECC."
    
            For the sake of safe, we will set the threshold with half the gf_len, and
            do not make it bigger the ECC strength.
    
       [1] count the bitflips of the current ECC chunk, assume it is N.
    
       [2] if the (N <= threshold) is true, we continue to read out the page with
           ECC disabled. and we count the bitflips again, assume it is N2.
           (We read out the whole page, not just a chunk, this makes the check
            more strictly, and make the code more simple.)
    
       [3] if the (N2 <= threshold) is true again, we can regard this is a erased
           page. This is because a real erased page is full of 0xFF(maybe also has
           several bitflips), while a page contains the 0xFF data will definitely
           has many bitflips in the ECC parity areas.
    
       [4] if the [3] fails, we can regard this is a page filled with the '0xFF'
           data.
    "
    
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    (cherry picked from commit ceb324a2914487aa517a6c70a06a20b5e3438fda)
  4. imx: imx7d: fix ahb clock mux 1

    falstaff84 authored and nxpfrankli committed May 5, 2016
    The clock parent of the AHB root clock when using mux option 1
    is the SYS PLL 270MHz clock. This is specified in  Table 5-11
    Clock Root Table of the i.MX 7Dual Applications Processor
    Reference Manual.
    
    While it could be a documentation error, the 270MHz parent is
    also mentioned in the boot ROM configuration in Table 6-28: The
    clock is by default at 135MHz due to a POST_PODF value of 1
    (=> divider of 2).
    
    Signed-off-by: Stefan Agner <stefan@agner.ch>
    (cherry picked from commit 8183b60202754d9d33ac1a2a68a5cc2cc4640fc6)
Commits on May 23, 2016
  1. MLK-12603: mtd: gpmi: may use legacy bch geometry in u-boot

    Han Xu authored and nxpfrankli committed Mar 28, 2016
    provide one config "CONFIG_NAND_MXS_BCH_LEGACY_GEO" to keep using legacy
    bch geometry.
    
    NOTICE: the feature must be enabled/disabled in both u-boot and kernel.
    
    Signed-off-by: Han Xu <han.xu@nxp.com>
  2. MLK-12371-2: imx: mx7dsabresd: fix POR reset failed after DDR enter r…

    Robin Gong authored and nxpfrankli committed Feb 3, 2016
    …etention
    
    Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR
    retention mode before uboot boot, so add this in DCD and plugin code.
    Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  3. MLK-12371-1: imx: mx7d_12x12_lpddr3_arm2: fix POR reset failed after …

    Robin Gong authored and nxpfrankli committed Feb 2, 2016
    …DDR enter retention
    
    Since DDR enter retention mode after kernel enter DSM mode, we have to exit DDR
    retention mode before uboot boot, so add this in DCD and plugin code. Meanwhile
    correct the HW_ANADIG_SNVS_MISC_CTRL setting to avoid touching other bits.
    
    Signed-off-by: Robin Gong <yibin.gong@nxp.com>
  4. MLK-12393: imx: mx6qamr2: update lpddr2 dcd programming aid settings

    Adrian Alonso authored and nxpfrankli committed Feb 9, 2016
    Adjust optimal valid clock cycles for 400Mhz operation
    Adjust valid clock cycles before self-refresh exit tCKSRX
    Adjust valid clock cycles after self-refresh entry tCKSRE
    
    Set MMDC1_MPZQHWCCTRL upper 16 bits to default reset value
    
    DDR calibration script
    http://sw-stash.freescale.net/projects/IMX/repos/ddr-scripts-rel/commits/040ee38ba9ad238fcb6053b663746d51321abb69
    
    Test result: Stress test passed.
    
    Signed-off-by: Adrian Alonso <adrian.alonso@nxp.com>
Commits on May 16, 2016
  1. MLK-12800 imx: mx7dsabresd: support revC

    MrVan committed May 16, 2016
    Add revC board support.
    
    Signed-off-by: Peng Fan <peng.fan@nxp.com>
    (cherry picked from commit 1f0bb3940876c9b0be6f3c5fc320dde81ced4d97)
    (cherry picked from commit e28beed75d8c501777f6eeadd127b1cb601115f8)
  2. MLK-12791 mx6qpsabresd: Change ENET TXCLK clock from PLL

    Ye Li
    Ye Li committed May 16, 2016
    In u-boot, i.MX6QP sabresd board uses 125Mhz ref clock from PHY,
    While kernel uses the clock from internal PLL by setting GPR5 bit 9.
    When doing warm reset in kernel, the GPR regigster is not reset, so
    the clock source still is the PLL. This causes ENET in u-boot can't work.
    
    In this patch, we change the u-boot to use internal PLL to align with
    kernel for i.MX6QP. This also fixes the ENET issue after kernel warm reset.
    
    Signed-off-by: Ye Li <ye.li@nxp.com>
    (cherry picked from commit 7f00c72e17e4e440df62aa4945a619fdbc9cfd8f)
Commits on May 9, 2016
  1. MLK-12748-3 imx: adjust imx7d lpddr3 lpsr exit flow

    Anson-Huang committed May 8, 2016
    On i.MX7D lpddr3, retention mode exit flow should restore
    more registers to make sure the ddr controller and ddr phy
    settings restored properly, otherwise, some of the boards
    can NOT pass memtester after retention mode exited.
    
    For LPSR mode, ddr resume flow is same as retention mode,
    just adjust it accordingly.
    
    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
  2. MLK-12748-2 imx: remove IOMUXC GPR setting for i.mx7d retention mode

    Anson-Huang committed May 4, 2016
    i.MX7D TO1.2 removes the DDR PADs retention mode setting
    in IOMUXC GPR, it is same as TO1.0, so only apply the
    IOMUXC GPR setting for TO1.1.
    
    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
  3. MLK-12748-1 imx: adjust i.mx7d standby voltage setting

    Anson-Huang committed May 6, 2016
    i.MX7D VDD_ARM/SOC standby voltage should be 0.95V,
    adding 25mV margin, so set it to 0.975V;
    
    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Commits on May 6, 2016
  1. MLK-12723 imx: Change the env offset on NAND to 60M

    Ye Li
    Ye Li committed May 5, 2016
    Current environment offset on NAND is 37MB, this will cause a alignment
    issue when erasing if nand erase block is 2MB. The saveenv is failed.
    
    => saveenv
    Saving Environment to NAND...
    Erasing NAND...
    Attempt to erase non block-aligned data
    
    Since the max erase block we supported is 4MB, adjust the env offset to 60MB,
    where is the last 4MB in 64MB reserved area for boot.
    
    Signed-off-by: Ye Li <ye.li@nxp.com>
    (cherry picked from commit 27e318ff148bdbeda0d8d80685dc5b4b159a3841)
Commits on Apr 29, 2016
  1. MLK-12705-2 imx7d: add build target for TO1.1

    Anson-Huang authored and nxpfrankli committed Apr 26, 2016
    Default build target supports TO1.0 and TO1.2,
    TO1.1 uses its own defconfig.
    
    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
  2. MLK-12705-1 ARM: imx: add support for i.MX7D TO1.2

    Anson-Huang authored and nxpfrankli committed Apr 26, 2016
    i.MX7D TO1.2 uses same DDR script as TO1.0,
    TO1.1 uses dedicated DDR script.
    
    Signed-off-by: Anson Huang <Anson.Huang@nxp.com>