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Support SSE 4.2 for the Singlepass compiler #2775

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merged 12 commits into from Feb 17, 2022

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batconjurer
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@batconjurer batconjurer commented Jan 31, 2022

Closes #2767

Description

This PR adds support for the SSE 4.2 instruction set in the singlepass compiler. Previously, only AVX was supported. This implementation may also work for SSE 4.1, but this should be double checked. It does use the blendvps instruction indroduced in SSE 4.1, so it cannot support any earlier SSE versions at present for sure.

The following are the main changes:

  • The assembler has changed from a Vec to a struct containing this as well as the corresponding CPU feature (indicating AVX/SSE4.2/...)
  • A set of SSE function macros have been added. To handle non-destructive operations, additional moves may be made before executing the corresponding SSE instruction if src1 != dst
  • A minor change to the EmitterX64 trait. It now has a function for returning a possible CPU feature.
  • The implementation of EmitterX64 for the assembler has obviously changed. It chooses the emitted assembly based on the CPU feature.

batconjurer added 2 commits Jan 30, 2022
…tween different simd instruction sets. Partial work on supporting SSE4.2
…s. Added >= SSE 4.1 implementation for emit_vblendvpd. Added some TODOs
@batconjurer batconjurer requested a review from syrusakbary as a code owner Jan 31, 2022
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@syrusakbary syrusakbary commented Feb 12, 2022

bors try

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@ptitSeb ptitSeb commented Feb 16, 2022

Can you rebase or merge your branch with current source code? The issue with the windows test has been fixed on master.

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@ptitSeb ptitSeb commented Feb 17, 2022

bors r+

bors bot added a commit that referenced this issue Feb 17, 2022
2775: Support SSE 4.2 for the Singlepass compiler r=ptitSeb a=batconjurer

Closes #2767 

# Description
This PR adds support for the SSE 4.2 instruction set in the singlepass compiler. Previously, only AVX was supported. This implementation may also work for SSE 4.1, but this should be double checked. It does use the `blendvps` instruction indroduced in SSE 4.1, so it cannot support any earlier SSE versions at present for sure. 

The following are the main changes:
 - The assembler has changed from a Vec<X64Relocation> to a struct containing this as well as the corresponding CPU feature (indicating AVX/SSE4.2/...)
 - A set of SSE function macros have been added. To handle non-destructive operations, additional moves may be made before executing the corresponding SSE instruction if `src1 != dst`
 - A minor change to the `EmitterX64` trait. It now has a function for returning a possible CPU feature.
 - The implementation of `EmitterX64` for the assembler has obviously changed. It chooses the emitted assembly based on the CPU feature.


Co-authored-by: R2D2 <jacob.turner870@gmail.com>
Co-authored-by: Jacob Turner <jacob.turner870@gmail.com>
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@bors bors bot commented Feb 17, 2022

Build failed:

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@ptitSeb ptitSeb commented Feb 17, 2022

sorry, code linter is complaining. you need to run cargo fmt --all.

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@ptitSeb ptitSeb commented Feb 17, 2022

bors r+

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@bors bors bot commented Feb 17, 2022

@bors bors bot merged commit fba8465 into wasmerio:master Feb 17, 2022
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ptitSeb added a commit that referenced this issue Feb 18, 2022
bors bot added a commit that referenced this issue Feb 18, 2022
2795: Fix singlepass Arm64 since #2775 r=Amanieu a=ptitSeb

# Description
PR #2775 broke Singlepass on Aarm64, since the test to check if the CPU have AVX or SSE 4.2 was done for all Architecture instead of being limited to x86_64.

Co-authored-by: ptitSeb <sebastien.chev@gmail.com>
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3 participants