diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C index 7fcc8719ded..d126020a645 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_cache_stopclocks.C @@ -30,26 +30,25 @@ // *HWP HWP Owner : David Du // *HWP Backup HWP Owner : Greg Still -// *HWP FW Owner : Sangeetha T S +// *HWP FW Owner : Amit Tendolkar // *HWP Team : PM // *HWP Consumed by : HB:PERV -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes //------------------------------------------------------------------------------ - #include #include #include #include -#include "p9_hcd_l2_stopclocks.H" -#include "p9_hcd_cache_stopclocks.H" +#include +#include +#include //------------------------------------------------------------------------------ // Constant Definitions //------------------------------------------------------------------------------ - enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS { CACHE_CLK_STOP_POLLING_HW_NS_DELAY = 10000, @@ -62,7 +61,7 @@ enum P9_HCD_CACHE_STOPCLOCKS_CONSTANTS //------------------------------------------------------------------------------ // Procedure: Quad Clock Stop //------------------------------------------------------------------------------ - +// See doxygen in header file fapi2::ReturnCode p9_hcd_cache_stopclocks( const fapi2::Target& i_target, @@ -99,7 +98,7 @@ p9_hcd_cache_stopclocks( // region including PBIEQ clock domain is being stopped, which // incidentally should always be the case for MPIPL l_data64.flush<0>(); - l_data64.setBit<30>(); + l_data64.setBit(); // Set bit 30 in EQ_QPPM_QCCR_SCOM2(100F01BF) Reg, Pulse to the // Powerbus logic in the Cache clock domain to request them to purge // their async buffers in preparation to power off the Quad @@ -113,9 +112,8 @@ p9_hcd_cache_stopclocks( // Acknowledgement from Powerbus that the buffers are empty // and can safely be fenced & clocked off. FAPI_TRY(fapi2::getScom(i_target, EQ_QPPM_QCCR_SCOM, l_data64)); - bool l_poll_data = l_data64.getBit<31>(); - if(l_poll_data == 1) + if(l_data64.getBit()) { break; } @@ -131,10 +129,11 @@ p9_hcd_cache_stopclocks( fapi2::QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT() .set_TARGET(i_target) .set_EQPPMQCCR(l_data64), - "QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit 31 not set."); + "QPPM_QCCR_PB_PURGE_DONE_LVL Reg bit _QPPM_QCCR_PB_PURGE_DONE_LVL not set."); + // Clear purge request l_data64.flush<0>(); - l_data64.setBit<30>(); + l_data64.setBit(); FAPI_TRY(fapi2::putScom(i_target, EQ_QPPM_QCCR_SCOM1, l_data64)); } @@ -142,7 +141,7 @@ p9_hcd_cache_stopclocks( l_attr_vdm_enabled)); FAPI_TRY(FAPI_ATTR_GET(fapi2::ATTR_CHIP_UNIT_POS, l_perv, l_attr_chip_unit_pos)); -// l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET; + // l_attr_chip_unit_pos = l_attr_chip_unit_pos - p9hcd::PERV_TO_QUAD_POS_OFFSET; l_attr_chip_unit_pos = l_attr_chip_unit_pos - 0x10; if (i_select_regions & p9hcd::CLK_REGION_EX0_L3) @@ -161,10 +160,9 @@ p9_hcd_cache_stopclocks( FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]"); FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64)); - if (!l_data64.getBit<15>()) + if (!l_data64.getBit()) { FAPI_DBG("Gracefully turn off power management, if fail, continue anyways"); - /// @todo RTC158181 suspend_pm() } FAPI_DBG("Check cache clock controller status"); @@ -182,15 +180,15 @@ p9_hcd_cache_stopclocks( FAPI_DBG("Check PERV fence status for access to CME via CPLT_CTRL1[4]"); FAPI_TRY(getScom(i_target, EQ_CPLT_CTRL1, l_temp64)); - if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0) + if (l_data64.getBit() == 0 && + l_temp64.getBit() == 0) { - /// @todo RTC158181 disable l2 snoop? disable lco? assert refresh quiesce? FAPI_DBG("Assert L3 pscom masks via RING_FENCE_MASK_LATCH_REG[4-9]"); FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l3mask_pscom)); } FAPI_DBG("Assert chiplet fence via NET_CTRL0[18]"); - FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(18))); + FAPI_TRY(putScom(i_target, EQ_NET_CTRL0_WOR, MASK_SET(EQ_NET_CTRL0_FENCE_EN))); // ------------------------------- // Stop L2 clocks @@ -247,17 +245,21 @@ p9_hcd_cache_stopclocks( FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); } - while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0)); + while((!l_data64.getBit()) && ((--l_loops1ms) != 0)); FAPI_ASSERT((l_loops1ms != 0), - fapi2::PMPROC_CACHECLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64), + fapi2::PMPROC_CACHECLKSTOP_TIMEOUT() + .set_TARGET(i_target) + .set_EQCPLTSTAT(l_data64), "Cache Clock Stop Timeout"); FAPI_DBG("Check cache clocks stopped"); FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); FAPI_ASSERT((((~l_data64) & l_region_clock) == 0), - fapi2::PMPROC_CACHECLKSTOP_FAILED().set_EQCLKSTAT(l_data64), + fapi2::PMPROC_CACHECLKSTOP_FAILED() + .set_TARGET(i_target) + .set_EQCLKSTAT(l_data64), "Cache Clock Stop Failed"); FAPI_DBG("Cache clocks stopped now"); @@ -266,7 +268,7 @@ p9_hcd_cache_stopclocks( // ------------------------------- FAPI_DBG("Assert vital fence via CPLT_CTRL1[3]"); - FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(3))); + FAPI_TRY(putScom(i_target, EQ_CPLT_CTRL1_OR, MASK_SET(EQ_CPLT_CTRL1_TC_VITL_REGION_FENCE))); l_region_fence = l_region_clock; @@ -356,4 +358,3 @@ fapi_try_exit: FAPI_INF("< // *HWP Backup HWP Owner : Greg Still -// *HWP FW Owner : Sangeetha T S +// *HWP FW Owner : Amit Tendolkar // *HWP Team : PM // *HWP Consumed by : HB:PERV -// *HWP Level : 2 +// *HWP Level : 3 #ifndef __P9_HCD_CACHE_STOPCLOCKS_H__ #define __P9_HCD_CACHE_STOPCLOCKS_H__ diff --git a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C index 73d4227c403..94383806528 100644 --- a/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C +++ b/src/import/chips/p9/procedures/hwp/cache/p9_hcd_l2_stopclocks.C @@ -30,10 +30,10 @@ // *HWP HWP Owner : David Du // *HWP Backup HWP Owner : Greg Still -// *HWP FW Owner : Sangeetha T S +// *HWP FW Owner : Amit Tendolkar // *HWP Team : PM // *HWP Consumed by : HB:PERV -// *HWP Level : 2 +// *HWP Level : 3 //------------------------------------------------------------------------------ // Includes @@ -43,7 +43,8 @@ #include #include #include -#include "p9_hcd_l2_stopclocks.H" +#include +#include //------------------------------------------------------------------------------ // Constant Definitions @@ -104,7 +105,7 @@ p9_hcd_l2_stopclocks( FAPI_DBG("Check PM_RESET_STATE_INDICATOR via GPMMR[15]"); FAPI_TRY(getScom(i_target, EQ_PPM_GPMMR_SCOM, l_data64)); - if (!l_data64.getBit<15>()) + if (!l_data64.getBit()) { FAPI_DBG("Gracefully turn off power management, if fail, continue anyways"); /// @todo RTC158181 suspend_pm() @@ -125,7 +126,8 @@ p9_hcd_l2_stopclocks( FAPI_DBG("Check PERV fence status for access to CME via CPLT_CTRL1[4]"); FAPI_TRY(getScom(i_target, EQ_CPLT_CTRL1, l_temp64)); - if (l_data64.getBit<4>() == 0 && l_temp64.getBit<4>() == 0) + if (!l_data64.getBit() && + !l_temp64.getBit()) { FAPI_DBG("Assert L2 pscom masks via RING_FENCE_MASK_LATCH_REG[2/3,10/11]"); FAPI_TRY(putScom(i_target, EQ_RING_FENCE_MASK_LATCH_REG, l_l2mask_pscom)); @@ -154,17 +156,22 @@ p9_hcd_l2_stopclocks( FAPI_TRY(getScom(i_target, EQ_CPLT_STAT0, l_data64)); } - while((l_data64.getBit<8>() != 1) && ((--l_loops1ms) != 0)); + while((!l_data64.getBit()) && + ((--l_loops1ms) != 0)); FAPI_ASSERT((l_loops1ms != 0), - fapi2::PMPROC_L2CLKSTOP_TIMEOUT().set_EQCPLTSTAT(l_data64), + fapi2::PMPROC_L2CLKSTOP_TIMEOUT() + .set_TARGET(i_target) + .set_EQCPLTSTAT(l_data64), "L2 Clock Stop Timeout"); FAPI_DBG("Check L2 clocks stopped"); FAPI_TRY(getScom(i_target, EQ_CLOCK_STAT_SL, l_data64)); FAPI_ASSERT((((~l_data64) & l_region_clock) == 0), - fapi2::PMPROC_L2CLKSTOP_FAILED().set_EQCLKSTAT(l_data64), + fapi2::PMPROC_L2CLKSTOP_FAILED() + .set_TARGET(i_target) + .set_EQCLKSTAT(l_data64), "L2 Clock Stop Failed"); FAPI_DBG("L2 clocks stopped now"); @@ -188,7 +195,9 @@ p9_hcd_l2_stopclocks( while(((l_data64 & l_l2sync_clock)) && ((--l_loops1ms) != 0)); FAPI_ASSERT((l_loops1ms != 0), - fapi2::PMPROC_CACHECLKSYNCDROP_TIMEOUT().set_EQPPMQACSR(l_data64), + fapi2::PMPROC_L2CLKSYNCDROP_TIMEOUT() + .set_TARGET(i_target) + .set_EQPPMQACSR(l_data64), "L2 Clock Sync Drop Timeout"); FAPI_DBG("L2 clock sync dones dropped"); @@ -212,4 +221,3 @@ fapi_try_exit: FAPI_INF("< // *HWP Backup HWP Owner : Greg Still -// *HWP FW Owner : Sangeetha T S +// *HWP FW Owner : Amit Tendolkar // *HWP Team : PM // *HWP Consumed by : HB:PERV -// *HWP Level : 2 #ifndef __P9_HCD_L2_STOPCLOCKS_H__ #define __P9_HCD_L2_STOPCLOCKS_H__ @@ -49,7 +48,7 @@ extern "C" { /// @brief Quad Clock Stop -/// @param [in] i_target TARGET_TYPE_EQ target +/// @param[in] i_target TARGET_TYPE_EQ target /// @return FAPI2_RC_SUCCESS if success, else error code fapi2::ReturnCode p9_hcd_l2_stopclocks( diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml index ea307155252..983f04ea913 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_cache_stopclocks_errors.xml @@ -38,7 +38,34 @@ cache clock stop failed. + TARGET EQCLKSTAT + + TARGET + HIGH + + + CODE + LOW + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + @@ -46,18 +73,71 @@ cache clock stop timed out. + TARGET EQCPLTSTAT + + TARGET + HIGH + + + CODE + LOW + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + RC_QPPM_QCCR_PB_PURGE_DONE_LVL_TIMEOUT - A timeout occured while waiting for Acknowledgement from + A timeout occured while waiting for Acknowledgement from Powerbus that the buffers are empty and can safely be fenced and clocked off TARGET EQPPMQCCR + + TARGET + HIGH + + + CODE + LOW + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + diff --git a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_l2_stopclocks_errors.xml b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_l2_stopclocks_errors.xml index 25a9fcdcd9b..8742e4aa102 100644 --- a/src/import/chips/p9/procedures/xml/error_info/p9_hcd_l2_stopclocks_errors.xml +++ b/src/import/chips/p9/procedures/xml/error_info/p9_hcd_l2_stopclocks_errors.xml @@ -31,6 +31,33 @@ L2 clock sync done drop timed out. EQPPMQACSR + TARGET + + TARGET + HIGH + + + CODE + LOW + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + @@ -38,7 +65,34 @@ L2 clock stop failed. + TARGET EQCLKSTAT + + TARGET + HIGH + + + CODE + LOW + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + @@ -46,7 +100,34 @@ L2 clock stop timed out. + TARGET EQCPLTSTAT + + TARGET + HIGH + + + CODE + LOW + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + + + + TARGET + + + + TARGET + TARGET_TYPE_CORE + +