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Pinned repositories
2,364 contributions in the last year
Activity overview
Contribution activity
December 2018
- whitequark/notifico Python
Created a pull request in YosysHQ/yosys that received 6 comments
Add a new opt_lut pass, which combines inefficiently packed LUTs
On iCE40, techmapping $alu always results in a SB_LUT4 cell with only 3 inputs used. This is inefficient and nothing later in the synthesis pipelin…
+646
−15
•
6
comments
- Extract ice40_unlut pass from ice40_opt
- gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
- lut2mux: handle 1-bit INIT constant in $lut cells
- rename: add -src, for inferring names from source locations
- synth_ice40: split `map_gates` off `fine`
- equiv_opt: new command, for verifying optimization passes
- write_verilog: inline internal cells that are used exactly once
- opt_lut: leave intact LUTs with cascade feeding module outputs
- write_verilog: correctly map RTLIL `sync init`
- select: print selection if a -assert-* flag causes an error
Created an issue in YosysHQ/nextpnr that received 9 comments
Mouse coordinates broken in floorplan view on HiDPI displays
See the screenshot. The popup is positioned correctly, the highlighted wire/cell uses ½ of the actual coordinate. (Also, everything appears as if …
9
comments
3
contributions
in private repositories
Dec 9