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@whitequark Boneless Arch is finalized, correct? In the upcoming week, I plan to modify the simulator so it has feature parity w/ the arch itself.
And maybe add async support. Idk how much good it'll do, since a CPU arch simulator doesn't have to wait for anything when simulating ALU/mem ops. But maybe it might be useful to schedule opcodes in the event loop between, say, simulated I/O peripherals. Thoughts?
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