Merge boneless_sim with Boneless-CPU

[cr1901]

Exactly what it says on the tin.

• setup.py working properly on my mind (both boneless and boneless_sim packages installed).
• Tests are properly discovered for both boneless and boneless_sim. The simulator tests pass on my end. The gateware tests on my machine fail with errors of the following form:

ERROR: test_XOR (boneless.gateware.test_core.BonelessTestCase)
----------------------------------------------------------------------
Traceback (most recent call last):
 File "C:\msys64\home\William\src\boneless-sim\boneless\gateware\test_core.py", line 14, in wrapper
   run_simulation(self.tb, case(self, self.tb), vcd_name="test.vcd")
 File "C:\msys64\home\william\src\nmigen\nmigen\compat\sim\__init__.py", line 19, in run_simulation
   with Simulator(fragment, vcd_file=open(vcd_name, "w") if vcd_name else None) as sim:
 File "C:\msys64\home\william\src\nmigen\nmigen\back\pysim.py", line 505, in __enter__
   var_type=var_type, size=var_size, init=var_init))
 File "C:\msys64\mingw64\lib\python3.6\site-packages\pyvcd-0.1.3-py3.6.egg\vcd\writer.py", line 144, in register_var
   raise ValueError('Invalid var_type "{}"'.format(var_type))
ValueError: Invalid var_type "string"

• Badges have been updated to point to your accounts.
• .travis.yml, readthedocs.yml unmodified, ready for your changes.
• .gitignore, setup.py merged.
• Stub README.md added. It is included by the top-level docs. I want to share the docs between boneless and boneless_sim.

[whitequark]

• Tests are properly discovered for both boneless and boneless_sim. The simulator tests pass on my end. The gateware tests on my machine fail with errors of the following form:

You need pyvcd>=0.1.4. This is in nmigen's dependencies, actually, not sure why it doesn't work.

[whitequark]

• setup.py working properly on my mind (both boneless and boneless_sim packages installed).

The package should be called boneless.simulator, similar to boneless.gateware.

[codecov-io]

Codecov Report

❗ No coverage uploaded for pull request base (master@32debb8). Click here to learn what that means.
The diff coverage is 99.43%.

@@            Coverage Diff            @@
##             master       #1   +/-   ##
=========================================
  Coverage          ?   96.34%           
=========================================
  Files             ?       13           
  Lines             ?     1257           
  Branches          ?        0           
=========================================
  Hits              ?     1211           
  Misses            ?       46           
  Partials          ?        0

Impacted Files	Coverage Δ
boneless/simulator/__init__.py	100% <100%> (ø)
boneless/simulator/test/test_insns.py	100% <100%> (ø)
boneless/simulator/test/test_idioms.py	100% <100%> (ø)
boneless/simulator/test/common.py	96.29% <96.29%> (ø)
boneless/simulator/test/test_except.py	97.61% <97.61%> (ø)
boneless/simulator/sim.py	99.56% <99.56%> (ø)

---

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[cr1901]

@whitequark Boneless Arch is finalized, correct? In the upcoming week, I plan to modify the simulator so it has feature parity w/ the arch itself.

And maybe add async support. Idk how much good it'll do, since a CPU arch simulator doesn't have to wait for anything when simulating ALU/mem ops. But maybe it might be useful to schedule opcodes in the event loop between, say, simulated I/O peripherals. Thoughts?

[whitequark]

Boneless Arch is finalized, correct? In the upcoming week, I plan to modify the simulator so it has feature parity w/ the arch itself.

Not yet.