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Boneless Manual Improvements #5

Merged
merged 27 commits into from
Apr 11, 2020
Merged

Boneless Manual Improvements #5

merged 27 commits into from
Apr 11, 2020

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tpwrules
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@tpwrules tpwrules commented Aug 25, 2019

This pull request is designed to improve and fix the manual for the Boneless architecture by clarifying and improving the Operation sections, adding material other than the instruction definitions, and ensuring that the manual documents Boneless's behavior as much as possible.

Tasks:

  • Define Operation syntax
  • Update Operations with new syntax
  • Fully document shift/rotate immediate encoding
  • Ensure shift/rotate Operation matches Boneless
  • Ensure flag generation for arithmetic instructions (in particular C and V) matches Boneless
  • Ensure jump conditions match CMP results
  • Document all programmer registers and logical variables in Operation
  • Categorize instructions incl. table of all the jumps

@whitequark
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Looks good so far!

@tpwrules
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tpwrules commented Nov 5, 2019

Some ideas for renaming the jump instructions.

1: rename JN to NOP. This gives the ISA a nice, 4 cycle NOP and avoids potential naming conflicts with the proposals below.

2: The various unconditional instructions will not be changed in this proposal. These instructions are J, JAL, JR, JRAL (why isn't this JALR though? it's spelled that way in RISC-V and MIPS), JST, JVT.

3: Prefix all the conditional jumps with B instead of J. This clearly indicates to the programmer that these instructions depend on the flags and may not always jump. [good]

<opinions based on my personal experience start here, I welcome additional perspectives!>

4: Rename the Sign flag to Negative. x86 has an S flag, but 6502, 68k, and ARM all use N and it's more natural to me. This would also change JS (jump if sign bit set) to JN, separating it from JSxx (jump if signed condition). [not happening, would make the opcodes weird]

5: Rename flags-based jumps to B<flag><Set or Clear>. This is how 6502, 68k, and ARM spell them and I am more familiar. Also avoids confusion with N for negative flag and N for not. Note that x86 spells them the Boneless way. [instead renaming to B<1 or 0> and keeping old ways also]

From To
JZ/JNZ, JE/JNE BZ/BNZ, BZ1/BZ0, BNE/BEQ
JS/JNS BS/BNS, BS1/BS0
JC/JNC BC/BNC, BC1/BC0
JO/JNO BV/BNV, BV1/BV0

6: Consider renaming signed and unsigned comparisons. I don't really love any of them, but presented below are some different styles for discussion. I might also like having signed vs. unsigned on the end instead of in the middle, in the vein of MIPS. [table below is good]

Note that the entries are signed/unsigned.

Condition Boneless x86 68k & ARM New Boneless
>= JSGE/JUGE jge/jae BGE/BHS BGES/BGEU
> JSGT/JUGT jg/ja BGT/BHI BGTS/BGTU
<= JSLE/JULE jle/jbe BLE/BLS BLES/BLEU
< JSLT/JULT jl/jb BLT/BLO BLTS/BLTU

@whitequark
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All looks good to me!

@tpwrules
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That should be the branch instructions updated. I want to add a quick reference chapter and then we should merge this.

@tpwrules
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Alright, that's all I wanted to do. Should be ready for merging.

@whitequark
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Can you update the spreadsheet too? Also, I think I'll squash the commits, so if you can write a concise summary I can put there that'd be great.

* improve ALU flag descriptions and related mnemonics (B -> C, O -> V)
* improve branch mnemonics (Jcc -> Bcc, new Bf0/Bf1 form, JN -> NOP)
* update manual and design spreadsheet with new mnemonics
* add Guide to Instruction Set section to manual, which lays out documentation conventions and summarizes the architecture and general behavior
* add Quick Reference section to manual, which lists and summarizes all of the instructions
* clarify instruction details in manual and correct various errors
@whitequark whitequark merged commit d86a557 into whitequark:master Apr 11, 2020
@whitequark
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Thanks for the PR, and sorry it's taken so long! I've added you to repository collaborators. Anything we have consensus on, feel free to just commit to master.

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2 participants