Bulk port of all gateware to nMigen compatibility layer.

software/glasgow/access/__init__.py

@@ -1,5 +1,5 @@
 from abc import ABCMeta, abstractmethod
-from migen import *
+from nmigen.compat import *
 
 from ..gateware.pads import Pads
 

software/glasgow/access/direct/multiplexer.py

@@ -1,5 +1,5 @@
 import logging
-from migen import *
+from nmigen.compat import *
 
 from .. import AccessMultiplexer, AccessMultiplexerInterface
 

software/glasgow/access/simulation/demultiplexer.py

@@ -1,5 +1,5 @@
 import asyncio
-from migen import *
+from nmigen.compat import *
 
 from ...support.logging import *
 from .. import AccessDemultiplexer, AccessDemultiplexerInterface

software/glasgow/access/simulation/multiplexer.py

@@ -1,5 +1,5 @@
-from migen import *
-from migen.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFOBuffered
+from nmigen.compat import *
+from nmigen.compat.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFOBuffered
 
 from .. import AccessMultiplexer, AccessMultiplexerInterface
 from ...gateware.fx2 import _FIFOWithFlush

software/glasgow/applet/__init__.py

@@ -75,7 +75,7 @@ async def run(self, args):
 import threading
 import inspect
 import json
-from migen.sim import *
+from nmigen.compat.sim import *
 
 from ..access.simulation import *
 from ..access.direct import *

software/glasgow/applet/benchmark/__init__.py

@@ -2,7 +2,7 @@
 import asyncio
 import struct
 import time
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 from ...gateware.lfsr import *

software/glasgow/applet/hd44780/__init__.py

@@ -9,8 +9,8 @@
 import math
 import argparse
 import logging
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 from .. import *
 

software/glasgow/applet/i2c_master/__init__.py

@@ -1,7 +1,7 @@
 import argparse
 import logging
 import math
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 from ...support.pyrepl import *

software/glasgow/applet/jtag/__init__.py

@@ -2,8 +2,8 @@
 import logging
 import asyncio
 from bitarray import bitarray
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 from .. import *
 from ...support.pyrepl import *

software/glasgow/applet/jtag_pinout/__init__.py

@@ -2,8 +2,8 @@
 import asyncio
 import random
 from functools import reduce
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 from .. import *
 from ...gateware.pads import *

software/glasgow/applet/nand_flash/__init__.py

@@ -2,8 +2,8 @@
 import logging
 import asyncio
 import struct
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 from .. import *
 from ...database.jedec import *

software/glasgow/applet/program_ice40/__init__.py

@@ -1,7 +1,7 @@
 import math
 import argparse
 import logging
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 

software/glasgow/applet/rgb_grabber/__init__.py

@@ -1,7 +1,7 @@
 import logging
 import math
-from migen import *
-from migen.genlib.cdc import *
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import *
 
 from .. import *
 

software/glasgow/applet/selftest/__init__.py

@@ -1,6 +1,6 @@
 import logging
 import asyncio
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 

software/glasgow/applet/shugart_floppy/__init__.py

@@ -299,8 +299,8 @@
 import itertools
 import crcmod
 import math
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 from .. import *
 from ...gateware.pads import *

software/glasgow/applet/spi_flash_avr/__init__.py

@@ -5,7 +5,7 @@
 import asyncio
 import argparse
 import collections
-from migen import *
+from nmigen.compat import *
 from fx2.format import autodetect, input_data, output_data
 
 from .. import *

software/glasgow/applet/spi_master/__init__.py

@@ -2,8 +2,8 @@
 import logging
 import asyncio
 import math
-from migen import *
-from migen.genlib.cdc import *
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import *
 
 from .. import *
 

software/glasgow/applet/swd/__init__.py

@@ -4,7 +4,7 @@
 import asyncio
 import struct
 import math
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 from ...gateware.pads import *

software/glasgow/applet/uart/__init__.py

@@ -2,7 +2,7 @@
 import sys
 import logging
 import asyncio
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 from ...gateware.pads import *

software/glasgow/applet/vga_output/__init__.py

@@ -1,5 +1,5 @@
 import logging
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 from ...gateware.pads import *

software/glasgow/applet/vga_terminal/__init__.py

@@ -2,7 +2,7 @@
 import asyncio
 import logging
 import argparse
-from migen import *
+from nmigen.compat import *
 
 from .. import *
 from ..vga_output import VGAOutputApplet

software/glasgow/applet/vga_terminal/cpu.py

@@ -33,7 +33,7 @@
 #   * JN   off       ≡  if(A < 0) PC ← PC + signext(off)
 #   * HLT            ≡  halt
 
-from migen import *
+from nmigen.compat import *
 
 
 __all__ = [

software/glasgow/gateware/__init__.py

@@ -1,5 +1,9 @@
 import functools
-from migen import *
+import os
+if os.getenv("NMIGEN"):
+    from nmigen.compat import run_simulation
+else:
+    from nmigen.compat import run_simulation
 
 
 __all__ = ["GatewareBuildError", "simulation_test"]

software/glasgow/gateware/analyzer.py

@@ -1,8 +1,8 @@
 from functools import reduce
 from collections import OrderedDict
-from migen import *
-from migen.genlib.fifo import _FIFOInterface, SyncFIFOBuffered
-from migen.genlib.coding import PriorityEncoder, PriorityDecoder
+from nmigen.compat import *
+from nmigen.compat.genlib.fifo import _FIFOInterface, SyncFIFOBuffered
+from nmigen.compat.genlib.coding import PriorityEncoder, PriorityDecoder
 
 
 __all__ = ["EventSource", "EventAnalyzer", "TraceDecodingError", "TraceDecoder"]
@@ -489,7 +489,6 @@ def is_done(self):
 # -------------------------------------------------------------------------------------------------
 
 import unittest
-from migen.fhdl import verilog
 
 from . import simulation_test
 

software/glasgow/gateware/boneless.py

@@ -1,4 +1,4 @@
-from migen import *
+from nmigen.compat import *
 
 from ..arch.boneless.opcode import *
 
@@ -92,7 +92,7 @@ def __init__(self, reset_addr, mem_rdport, mem_wrport, ext_port=None, simulation
             ext_port = _StubMemoryPort("ext")
 
         def decode(v):
-            d = Signal.like(v)
+            d = Signal.like(v, src_loc_at=1)
             self.comb += d.eq(v)
             return d
 
@@ -787,7 +787,7 @@ def test_JSLE(self, tb):
 # -------------------------------------------------------------------------------------------------
 
 import argparse
-from migen.fhdl import verilog
+from nmigen.compat.fhdl import verilog
 
 
 class BonelessTestbench(Module):
@@ -824,21 +824,21 @@ def __init__(self, has_pins=False):
 
     if args.type == "alu":
         tb  = _ALU(16)
-        ios = {tb.s_a, tb.s_b, tb.s_o, tb.c_sel}
+        ios = (tb.s_a, tb.s_b, tb.s_o, tb.c_sel)
 
     if args.type == "sru":
         tb  = _SRU(16)
-        ios = {tb.s_i, tb.s_c, tb.r_o, tb.c_ld, tb.c_dir}
+        ios = (tb.s_i, tb.s_c, tb.r_o, tb.c_ld, tb.c_dir)
 
     if args.type == "bus":
         tb  = BonelessTestbench()
-        ios = {tb.ext_port.adr,
+        ios = (tb.ext_port.adr,
                tb.ext_port.re, tb.ext_port.dat_r,
-               tb.ext_port.we, tb.ext_port.dat_w}
+               tb.ext_port.we, tb.ext_port.dat_w)
 
     if args.type == "pins":
         tb  = BonelessTestbench(has_pins=True)
-        ios = {tb.pins}
+        ios = (tb.pins,)
 
     design = verilog.convert(tb, ios=ios, name="boneless")
     design.write("boneless.v")

software/glasgow/gateware/fx2.py

@@ -23,10 +23,10 @@
 # FIFOADR->FLAG                 10.7
 # FIFOADR->FIFODATA             14.3
 
-from migen import *
-from migen.genlib.cdc import MultiReg
-from migen.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFO, SyncFIFOBuffered
-from migen.genlib.resetsync import AsyncResetSynchronizer
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
+from nmigen.compat.genlib.fifo import _FIFOInterface, AsyncFIFO, SyncFIFO, SyncFIFOBuffered
+from nmigen.compat.genlib.resetsync import AsyncResetSynchronizer
 
 
 __all__ = ["FX2Arbiter"]

software/glasgow/gateware/i2c.py

@@ -1,7 +1,7 @@
 # I2C reference: https://www.nxp.com/docs/en/user-guide/UM10204.pdf
 
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 
 __all__ = ['I2CSlave']
@@ -397,7 +397,6 @@ def __init__(self, pads):
 # -------------------------------------------------------------------------------------------------
 
 import unittest
-from migen.fhdl import verilog
 
 from . import simulation_test
 
@@ -856,8 +855,3 @@ class _DummyPads(Module):
     def __init__(self):
         self.scl_t = TSTriple()
         self.sda_t = TSTriple()
-
-
-if __name__ == "__main__":
-    verilog.convert(I2CMaster(_DummyPads(), 16)).write("i2cmaster.v")
-    verilog.convert(I2CSlave(_DummyPads())).write("i2cslave.v")

software/glasgow/gateware/lfsr.py

@@ -1,4 +1,4 @@
-from migen import *
+from nmigen.compat import *
 
 
 __all__ = ["LinearFeedbackShiftRegister"]
@@ -54,7 +54,6 @@ def generate(self):
 # -------------------------------------------------------------------------------------------------
 
 import unittest
-from migen.fhdl import verilog
 
 from . import simulation_test
 

software/glasgow/gateware/mpsse.py

@@ -2,8 +2,8 @@
 # http://www.ftdichip.com/Support/Documents/AppNotes/AN_135_MPSSE_Basics.pdf
 # http://www.ftdichip.com/Support/Documents/AppNotes/ AN_108_Command_Processor_for_MPSSE_and_MCU_Host_Bus_Emulation_Modes.pdf
 
-from migen import *
-from migen.genlib.cdc import MultiReg
+from nmigen.compat import *
+from nmigen.compat.genlib.cdc import MultiReg
 
 
 __all__ = ['MPSSE']
@@ -427,7 +427,6 @@ def __init__(self, pads):
 # -------------------------------------------------------------------------------------------------
 
 import unittest
-from migen.fhdl import verilog
 
 from . import simulation_test
 
@@ -740,13 +739,3 @@ def test_write_single_byte_clkwrong(self, tb):
         self.assertEqual((yield from tb.recv_tdi(8, pos=False)), 0xA5)
         yield
         self.assertEqual((yield tb.tck.o), 0)
-
-
-if __name__ == "__main__":
-    tck = TSTriple()
-    tdi = TSTriple()
-    tdo = TSTriple()
-    tms = TSTriple()
-    engine = MPSSE([tck, tdi, tdo, tms])
-
-    verilog.convert(engine).write("mpsse.v")

software/glasgow/gateware/pads.py

@@ -1,4 +1,4 @@
-from migen import *
+from nmigen.compat import *
 
 
 __all__ = ['Pads']
@@ -82,7 +82,7 @@ def _add_elem(self, elem, name=None, index=None):
 # -------------------------------------------------------------------------------------------------
 
 import unittest
-from migen.fhdl.specials import Tristate
+from nmigen.compat.fhdl.specials import Tristate
 
 
 class PadsTestCase(unittest.TestCase):

software/glasgow/gateware/platform/lattice.py

@@ -1,4 +1,4 @@
-from migen import *
+from nmigen.compat import *
 
 from .. import GatewareBuildError
 from ..pll import PLL