diff --git a/Modelica/Electrical/Analog/Lines/TLine1.mo b/Modelica/Electrical/Analog/Lines/TLine1.mo
index 154414943d..144733c77f 100644
--- a/Modelica/Electrical/Analog/Lines/TLine1.mo
+++ b/Modelica/Electrical/Analog/Lines/TLine1.mo
@@ -6,8 +6,8 @@ model TLine1
   parameter SI.Resistance Z0(start=1)
     "Characteristic impedance";
   parameter SI.Time TD(start=1) "Transmission delay";
-  SI.Voltage er(start=0);
-  SI.Voltage es(start=0);
+  SI.Voltage er(start=0) "Reflected voltage wave";
+  SI.Voltage es(start=0) "Incident voltage wave";
 equation
   assert(Z0 > 0, "Z0 has to be positive");
   assert(TD > 0, "TD has to be positive");
diff --git a/Modelica/Electrical/Analog/Lines/TLine2.mo b/Modelica/Electrical/Analog/Lines/TLine2.mo
index d1d765eba9..e59fc97769 100644
--- a/Modelica/Electrical/Analog/Lines/TLine2.mo
+++ b/Modelica/Electrical/Analog/Lines/TLine2.mo
@@ -7,8 +7,8 @@ model TLine2
     "Characteristic impedance";
   parameter SI.Frequency F(start=1) "Frequency";
   parameter Real NL(start=1) "Normalized length";
-  SI.Voltage er(start=0);
-  SI.Voltage es(start=0);
+  SI.Voltage er(start=0) "Reflected voltage wave";
+  SI.Voltage es(start=0) "Incident voltage wave";
 protected
   parameter SI.Time TD=NL/F;
 equation
diff --git a/Modelica/Electrical/Analog/Lines/TLine3.mo b/Modelica/Electrical/Analog/Lines/TLine3.mo
index 479f2967a4..1563090e57 100644
--- a/Modelica/Electrical/Analog/Lines/TLine3.mo
+++ b/Modelica/Electrical/Analog/Lines/TLine3.mo
@@ -4,8 +4,8 @@ model TLine3
   extends Modelica.Electrical.Analog.Interfaces.TwoPort;
   parameter SI.Resistance Z0(start=1) "Natural impedance";
   parameter SI.Frequency F(start=1) "Frequency";
-  SI.Voltage er(start=0);
-  SI.Voltage es(start=0);
+  SI.Voltage er(start=0) "Reflected voltage wave";
+  SI.Voltage es(start=0) "Incident voltage wave";
 protected
   parameter SI.Time TD=1/F/4;
 equation