Revision 1.0

wojciechk8 · Apr 26, 2017 · bd1c6d7 · bd1c6d7
1 parent db15e76
commit bd1c6d7
Show file tree

Hide file tree

Showing 8 changed files with 14 additions and 10 deletions.
diff --git a/changelog b/changelog
@@ -17,4 +17,8 @@ REV 0.2 ----------------------------------------------------------------
   1. Corrected placement of some components
   2. Changed RPi connector footprint
 
-
+REV 1.0 ----------------------------------------------------------------
+  Schematic:
+  1. Changed USART connection to USART1 (PA9, PA10), so now it's
+     possible to use the internal bootloader.
+  2. Changed location of testpoint TP41
diff --git a/pcb/mmdvm_pog.pcb b/pcb/mmdvm_pog.pcb
@@ -3084,8 +3084,8 @@ Layer(1 "top" "copper")
 	Line[27.6330mm 30.7010mm 27.6330mm 30.9550mm 0.2500mm 0.5000mm "clearline"]
 	Line[35.5070mm 20.9220mm 32.5860mm 18.0010mm 0.2500mm 0.5000mm "clearline"]
 	Line[32.5860mm 18.0010mm 29.6650mm 18.0010mm 0.2500mm 0.5000mm "clearline"]
-	Line[28.0140mm 17.7579mm 28.0031mm 17.7579mm 0.2500mm 0.5000mm "clearline"]
-	Line[28.0031mm 17.7579mm 26.9980mm 18.7630mm 0.2500mm 0.5000mm "clearline"]
+	Line[28.0140mm 699.13mil 28.0031mm 699.13mil 0.2500mm 0.5000mm "clearline"]
+	Line[28.0031mm 699.13mil 26.9980mm 18.7630mm 0.2500mm 0.5000mm "clearline"]
 	Line[28.9030mm 24.3510mm 28.9030mm 21.0490mm 0.2500mm 0.5000mm "clearline"]
 	Line[28.3950mm 24.0970mm 28.3950mm 20.7950mm 0.2500mm 0.5000mm "clearline"]
 	Line[28.3950mm 20.7950mm 29.7920mm 19.3980mm 0.2500mm 0.5000mm "clearline"]
@@ -3101,7 +3101,7 @@ Layer(1 "top" "copper")
 	Line[31.1890mm 9.8730mm 31.1890mm 16.9850mm 0.2500mm 0.5000mm "clearline"]
 	Line[29.9190mm 18.5090mm 32.3320mm 18.5090mm 0.2500mm 0.5000mm "clearline"]
 	Line[32.3320mm 18.5090mm 34.8839mm 21.0609mm 0.2500mm 0.5000mm "clearline"]
-	Line[34.8839mm 21.0609mm 34.8839mm 24.1135mm 0.2500mm 0.5000mm "clearline"]
+	Line[34.8839mm 21.0609mm 34.8839mm 949.35mil 0.2500mm 0.5000mm "clearline"]
 	Line[34.8720mm 18.7630mm 32.5860mm 16.4770mm 0.2500mm 0.5000mm "clearline"]
 	Line[32.5860mm 16.4770mm 32.2050mm 16.4770mm 0.2500mm 0.5000mm "clearline"]
 	Line[32.2050mm 10.1270mm 32.2050mm 16.4770mm 0.2500mm 0.5000mm "clearline"]
@@ -3111,8 +3111,8 @@ Layer(1 "top" "copper")
 	Line[25.6010mm 19.7790mm 22.4260mm 19.7790mm 0.2500mm 0.5000mm "clearline"]
 	Line[22.0450mm 20.1600mm 22.4260mm 19.7790mm 0.2500mm 0.5000mm "clearline"]
 	Text[25.8110mm 55.7200mm 0 115 "(C) WK" "clearline"]
-	Text[58.5770mm 46.9570mm 1 105 "DC1713" "clearline"]
-	Text[57.1800mm 46.9570mm 1 105 "R0.2" "clearline"]
+	Text[58.5770mm 46.9570mm 1 105 "DC1717" "clearline"]
+	Text[57.1800mm 46.9570mm 1 105 "R1.0" "clearline"]
 	Text[2.7410mm 23.9260mm 0 105 "IGN" "clearline"]
 	Text[2.6140mm 26.4660mm 0 105 "PTT" "clearline"]
 	Text[1.4710mm 29.0060mm 0 105 "TXRX" "clearline"]
@@ -4065,8 +4065,8 @@ Layer(7 "top silk" "silk")
 	Line[297.05mil 56.4192mm 330.90mil 54.7670mm 6.63mil 20.00mil "clearline"]
 	Line[270.73mil 56.4192mm 297.05mil 56.4192mm 6.63mil 20.00mil "clearline"]
 	Text[25.8110mm 55.7200mm 0 115 "(C) WK" "clearline"]
-	Text[58.5770mm 46.9570mm 1 105 "DC1713" "clearline"]
-	Text[57.1800mm 46.9570mm 1 105 "R0.2" "clearline"]
+	Text[58.5770mm 46.9570mm 1 105 "DC1717" "clearline"]
+	Text[57.1800mm 46.9570mm 1 105 "R1.0" "clearline"]
 	Text[2.7410mm 23.9260mm 0 105 "IGN" "clearline"]
 	Text[2.6140mm 26.4660mm 0 105 "PTT" "clearline"]
 	Text[1.4710mm 29.0060mm 0 105 "TXRX" "clearline"]

diff --git a/pcb/mmdvm_pog.pdf b/pcb/mmdvm_pog.pdf
diff --git a/pcb/mmdvm_pog.png b/pcb/mmdvm_pog.png
diff --git a/pcb/mmdvm_pog.ps b/pcb/mmdvm_pog.ps
diff --git a/pcb/mmdvm_pog_assy.pdf b/pcb/mmdvm_pog_assy.pdf
diff --git a/sch/mmdvm_pog.pdf b/sch/mmdvm_pog.pdf
diff --git a/sch/mmdvm_pog.sch b/sch/mmdvm_pog.sch
@@ -13,9 +13,9 @@ page=1
 T 75900 40700 5 14 1 1 0 4 1
 pageof=1
 T 75400 42300 5 14 1 1 0 4 1
-revision=0.2
+revision=1.0
 T 75400 41500 5 14 1 1 0 4 1
-date=28-03-2017
+date=26-04-2017
 T 69700 40700 5 14 1 1 0 1 1
 author=Wojciech Krutnik
 }