diff --git a/Makefile b/Makefile
index dc9b95d42f..7d329a4293 100644
--- a/Makefile
+++ b/Makefile
@@ -1,16 +1,18 @@
-CROSS_COMPILE:=arm-none-eabi-
-CC:=$(CROSS_COMPILE)gcc
-LD:=$(CROSS_COMPILE)gcc
-AS:=$(CROSS_COMPILE)gcc
-OBJCOPY:=$(CROSS_COMPILE)objcopy
-SIZE:=$(CROSS_COMPILE)size
-BOOT0_OFFSET?=`cat include/target.h |grep WOLFBOOT_PARTITION_BOOT_ADDRESS | head -1 | sed -e "s/.*[ ]//g"`
-BOOT_IMG?=test-app/image.bin
+## wolfBoot Makefile
+#
+# Configure by passing alternate values
+# via environment variables.
+#
+# Default values:
+ARCH?=ARM
+TARGET?=stm32f4
 SIGN?=ED25519
 TARGET?=stm32f4
 KINETIS?=$(HOME)/src/FRDM-K64F
+KINETIS_CPU=MK64FN1M0VLL12
 KINETIS_DRIVERS?=$(KINETIS)/devices/MK64F12
 KINETIS_CMSIS?=$(KINETIS)/CMSIS
+FREEDOM_E_SDK?=$(HOME)/src/freedom-e-sdk
 DEBUG?=0
 VTOR?=1
 CORTEX_M0?=0
@@ -19,14 +21,20 @@ EXT_FLASH?=0
 SPI_FLASH?=0
 ALLOW_DOWNGRADE?=0
 NVM_FLASH_WRITEONCE?=0
-LSCRIPT:=hal/$(TARGET).ld
+V?=0
+SPMATH?=1
+
+
 
+## Initializers
+CFLAGS:=-D__WOLFBOOT 
+LSCRIPT:=hal/$(TARGET).ld
+LDFLAGS:=-T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=wolfboot.map -ffreestanding -nostartfiles 
 OBJS:= \
 ./hal/$(TARGET).o \
 ./src/loader.o \
 ./src/string.o \
 ./src/crypto.o \
-./src/wolfboot.o \
 ./src/image.o \
 ./src/libwolfboot.o \
 ./lib/wolfssl/wolfcrypt/src/sha256.o \
@@ -34,53 +42,44 @@ OBJS:= \
 ./lib/wolfssl/wolfcrypt/src/wolfmath.o \
 ./lib/wolfssl/wolfcrypt/src/fe_low_mem.o
 
-## Target specific configuration
-ifeq ($(TARGET),samr21)
-  CORTEX_M0=1
-endif
+## Architecture/CPU configuration
+include arch.mk
+
+
+## DSA Settings
 
-## Signature
 ifeq ($(SIGN),ECC256)
   KEYGEN_TOOL=tools/ecc256/ecc256_keygen
   SIGN_TOOL=tools/ecc256/ecc256_sign
   PRIVATE_KEY=ecc256.der
+  OBJS+= \
+    $(ECC_EXTRA_OBJS) \
+    $(MATH_OBJS) \
+	./lib/wolfssl/wolfcrypt/src/ecc.o \
+	./lib/wolfssl/wolfcrypt/src/ge_low_mem.o \
+	./lib/wolfssl/wolfcrypt/src/memory.o \
+	./lib/wolfssl/wolfcrypt/src/wc_port.o \
+    ./src/ecc256_pub_key.o \
+    ./src/xmalloc.o
+  CFLAGS+=-DWOLFBOOT_SIGN_ECC256 -DXMALLOC_USER $(ECC_EXTRA_CFLAGS)
 else
   KEYGEN_TOOL=tools/ed25519/ed25519_keygen
   SIGN_TOOL=tools/ed25519/ed25519_sign
   PRIVATE_KEY=ed25519.der
+  OBJS+= ./lib/wolfssl/wolfcrypt/src/sha512.o \
+	./lib/wolfssl/wolfcrypt/src/ed25519.o \
+	./lib/wolfssl/wolfcrypt/src/ge_low_mem.o \
+    ./src/ed25519_pub_key.o
+  CFLAGS+=-DWOLFBOOT_SIGN_ED25519 -nostdlib -DWOLFSSL_STATIC_MEMORY
+  LDFLAGS+=-nostdlib
 endif
 
-MATH_OBJS:=./lib/wolfssl/wolfcrypt/src/sp_int.o
-
-ifeq ($(CORTEX_M0),1)
-  CFLAGS:=-mcpu=cortex-m0
-  MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
-else
-  ifeq ($(NO_ASM),1)
-    MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
-    CFLAGS:=-mcpu=cortex-m3
-  else
-    CFLAGS:=-mcpu=cortex-m3 -D__WOLFBOOT -DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM -fomit-frame-pointer
-    MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
-  endif
-endif
-
-ifeq ($(FASTMATH),1)
-  MATH_OBJS:=./lib/wolfssl/wolfcrypt/src/integer.o
-  CFLAGS+=-DUSE_FAST_MATH
-endif
 
-CFLAGS+=-mthumb -Wall -Wextra -Wno-main -Wstack-usage=1024 -ffreestanding -Wno-unused \
-	-I. -Ilib/bootutil/include -Iinclude/ -Ilib/wolfssl -nostartfiles \
+CFLAGS+=-Wall -Wextra -Wno-main -Wstack-usage=1024 -ffreestanding -Wno-unused \
+	-I. -Iinclude/ -Ilib/wolfssl -nostartfiles \
 	-DWOLFSSL_USER_SETTINGS \
-	-mthumb -mlittle-endian -mthumb-interwork \
 	-DPLATFORM_$(TARGET)
 
-ifeq ($(TARGET),kinetis)
-  CFLAGS+= -I$(KINETIS_DRIVERS)/drivers -I$(KINETIS_DRIVERS) -DCPU_MK64FN1M0VLL12 -I$(KINETIS_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1
-  OBJS+= $(KINETIS_DRIVERS)/drivers/fsl_clock.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_flash.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_cache.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_controller.o
-endif
-
 ifeq ($(SPI_FLASH),1)
    EXT_FLASH=1
    CFLAGS+= -DSPI_FLASH=1
@@ -91,7 +90,6 @@ ifeq ($(EXT_FLASH),1)
   CFLAGS+= -DEXT_FLASH=1 -DPART_UPDATE_EXT=1 -DPART_SWAP_EXT=1
 endif
 
-
 ifeq ($(ALLOW_DOWNGRADE),1)
   CFLAGS+= -DALLOW_DOWNGRADE
 endif
@@ -100,29 +98,7 @@ ifeq ($(NVM_FLASH_WRITEONCE),1)
   CFLAGS+= -DNVM_FLASH_WRITEONCE
 endif
 
-LDFLAGS:=-T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=wolfboot.map -ffreestanding -nostartfiles -mcpu=cortex-m3 -mthumb
-ASFLAGS:=$(CFLAGS)
 
-ifeq ($(SIGN),ED25519)
-  OBJS+= ./lib/wolfssl/wolfcrypt/src/sha512.o \
-	./lib/wolfssl/wolfcrypt/src/ed25519.o \
-	./lib/wolfssl/wolfcrypt/src/ge_low_mem.o \
-    ./src/ed25519_pub_key.o
-  CFLAGS+=-DWOLFBOOT_SIGN_ED25519 -nostdlib -DWOLFSSL_STATIC_MEMORY
-  LDFLAGS+=-nostdlib
-endif
-
-ifeq ($(SIGN),ECC256)
-  OBJS+= \
-    $(MATH_OBJS) \
-	./lib/wolfssl/wolfcrypt/src/ecc.o \
-	./lib/wolfssl/wolfcrypt/src/ge_low_mem.o \
-	./lib/wolfssl/wolfcrypt/src/memory.o \
-	./lib/wolfssl/wolfcrypt/src/wc_port.o \
-    ./src/ecc256_pub_key.o \
-    ./src/xmalloc.o
-  CFLAGS+=-DWOLFBOOT_SIGN_ECC256 -DXMALLOC_USER
-endif
 
 ifeq ($(DEBUG),1)
     CFLAGS+=-O0 -g -ggdb3 -DDEBUG=1
@@ -130,57 +106,71 @@ else
     CFLAGS+=-Os
 endif
 
+ifeq ($(V),0)
+  Q=@
+endif
+
 ifeq ($(VTOR),0)
     CFLAGS+=-DNO_VTOR
 endif
 
+ASFLAGS:=$(CFLAGS)
 
 all: factory.bin
 
-
 wolfboot.bin: wolfboot.elf
-	$(OBJCOPY) -O binary $^ $@
-	$(SIZE) wolfboot.elf
+	@echo "\t[BIN] $@"	
+	$(Q)$(OBJCOPY) -O binary $^ $@
 
 wolfboot.hex: wolfboot.elf
-	$(OBJCOPY) -O ihex $^ $@
+	@echo "\t[HEX] $@"	
+	$(Q)$(OBJCOPY) -O ihex $^ $@
 
 align: wolfboot-align.bin
 
-wolfboot-align.bin: wolfboot.elf
-	$(OBJCOPY) -O binary $^ $@ --pad-to=$(BOOT0_OFFSET) --gap-fill=255
-	$(SIZE) wolfboot.elf
-
+wolfboot-align.bin: wolfboot.bin
+	@cat include/target.h |grep WOLFBOOT_PARTITION_BOOT_ADDRESS | head -1 | sed -e "s/.*[ ]//g" > .wolfboot-offset
+	@printf "%d" `cat .wolfboot-offset` > .wolfboot-offset
+	@printf "%d" $(ARCH_FLASH_OFFSET) >.wolfboot-arch-offset
+	@expr `cat .wolfboot-offset` - `cat .wolfboot-arch-offset` >.wolfboot-partition-size
+	@dd if=/dev/zero bs=`cat .wolfboot-partition-size` count=1 2>/dev/null | tr "\000" "\377" > $(@)
+	@rm -f .wolfboot-partition-size .wolfboot-offset .wolfboot-arch-offset
+	@dd if=$^ of=$(@) conv=notrunc 2>/dev/null
+	@echo
+	@echo "\t[SIZE]"
+	@$(SIZE) wolfboot.elf
+	@echo
 
 test-app/image.bin:
-	make -C test-app TARGET=$(TARGET) EXT_FLASH=$(EXT_FLASH) SPI_FLASH=$(SPI_FLASH)
+	@make -C test-app TARGET=$(TARGET) EXT_FLASH=$(EXT_FLASH) SPI_FLASH=$(SPI_FLASH) ARCH=$(ARCH) V=$(V) \
+	KINETIS=$(KINETIS) KINETIS_CPU=$(KINETIS_CPU) KINETIS_DRIVERS=$(KINETIS_DRIVERS) \
+	KINETIS_CMSIS=$(KINETIS_CMSIS) NVM_FLASH_WRITEONCE=$(NVM_FLASH_WRITEONCE) \
+	FREEDOM_E_SDK=$(FREEDOM_E_SDK)
+	@rm -f src/*.o hal/*.o
 
 include tools/test.mk
 
 tools/ed25519/ed25519_sign:
-	make -C tools/ed25519
+	@make -C tools/ed25519
 
 tools/ecc256/ecc256_sign:
-	make -C tools/ecc256
+	@make -C tools/ecc256
 
 ed25519.der: tools/ed25519/ed25519_sign
-	tools/ed25519/ed25519_keygen src/ed25519_pub_key.c
+	@tools/ed25519/ed25519_keygen src/ed25519_pub_key.c
 
 ecc256.der: tools/ecc256/ecc256_sign
-	tools/ecc256/ecc256_keygen src/ecc256_pub_key.c
+	@tools/ecc256/ecc256_keygen src/ecc256_pub_key.c
 
 factory.bin: $(BOOT_IMG) wolfboot-align.bin $(SIGN_TOOL) $(PRIVATE_KEY)
-	$(SIGN_TOOL) $(BOOT_IMG) $(PRIVATE_KEY) 1
-	cat wolfboot-align.bin $(BOOT_IMG).v1.signed > $@
-
-second.img: $(BOOT_IMG) wolfboot-align.bin $(SIGN_TOOL) $(PRIVATE_KEY)
-	$(SIGN_TOOL) $(BOOT_IMG) $(PRIVATE_KEY) 1 65536
-	$(SIGN_TOOL) $(BOOT_IMG) $(PRIVATE_KEY) 2
-	cat wolfboot-align.bin $(BOOT_IMG).v1.signed $(BOOT_IMG).v2.signed > $@
+	@echo "\t[SIGN] $(BOOT_IMG)"
+	$(Q)$(SIGN_TOOL) $(BOOT_IMG) $(PRIVATE_KEY) 1 >/dev/null
+	@echo "\t[MERGE] $@"
+	@cat wolfboot-align.bin $(BOOT_IMG).v1.signed > $@
 
 wolfboot.elf: $(OBJS) $(LSCRIPT)
-	grep stat $(OBJS)
-	$(LD) $(LDFLAGS) -Wl,--start-group $(OBJS) -Wl,--end-group -o $@
+	@echo "\t[LD] $@"
+	$(Q)$(LD) $(LDFLAGS) -Wl,--start-group $(OBJS) -Wl,--end-group -o $@
 
 src/ed25519_pub_key.c: ed25519.der
 
@@ -189,13 +179,23 @@ src/ecc256_pub_key.c: ecc256.der
 keys: $(PRIVATE_KEY)
 	
 clean:
-	rm -f *.bin *.elf $(OBJS) wolfboot.map *.bin  *.hex hal/*.o
-	make -C test-app clean
+	@find . -type f -name "*.o" | xargs -x rm -f
+	@rm -f *.bin *.elf wolfboot.map *.bin  *.hex
+	@make -C test-app clean
 
 distclean: clean
-	make -C tools/ed25519 clean
-	make -C tools/ecc256 clean
-	rm -f *.pem *.der tags ./src/ed25519_pub_key.c ./src/ecc256_pub_key.c
+	@make -C tools/ed25519 clean
+	@make -C tools/ecc256 clean
+	@rm -f *.pem *.der tags ./src/ed25519_pub_key.c ./src/ecc256_pub_key.c
+
+
+%.o:%.c
+	@echo "\t[CC-$(ARCH)] $@"
+	$(Q)$(CC) $(CFLAGS) -c -o $@ $^
+
+%.o:%.S
+	@echo "\t[AS-$(ARCH)] $@"
+	$(Q)$(CC) $(CFLAGS) -c -o $@ $^
 
 FORCE: 
 
diff --git a/arch.mk b/arch.mk
new file mode 100644
index 0000000000..6f92dcb174
--- /dev/null
+++ b/arch.mk
@@ -0,0 +1,73 @@
+## CPU Architecture selection via $ARCH
+
+# check for FASTMATH or SP_MATH
+ifeq ($(SPMATH),1)
+  MATH_OBJS:=./lib/wolfssl/wolfcrypt/src/sp_int.o
+else
+  MATH_OBJS:=./lib/wolfssl/wolfcrypt/src/integer.o
+endif
+
+## ARM
+ifeq ($(ARCH),ARM)
+  CROSS_COMPILE:=arm-none-eabi-
+  CFLAGS+=-mthumb -mlittle-endian -mthumb-interwork -DARCH_ARM
+  LDFLAGS+=-mthumb -mlittle-endian -mthumb-interwork
+  OBJS+=src/boot_arm.o
+  ARCH_FLASH_OFFSET=0x0
+
+  ## Cortex-M CPU
+  ifeq ($(CORTEX_M0),1)
+    CFLAGS+=-mcpu=cortex-m0
+    LDFLAGS+=-mcpu=cortex-m0
+    ifeq ($(SPMATH),1)
+      MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
+    endif
+  else
+    ifeq ($(NO_ASM),1)
+      ifeq ($(SPMATH),1)
+        MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_c32.o
+      endif
+      CFLAGS+=-mcpu=cortex-m3
+      LDFLAGS+=-mcpu=cortex-m3
+    else
+      CFLAGS+=-mcpu=cortex-m3 -fomit-frame-pointer
+      LDFLAGS+=-mcpu=cortex-m3
+      ifeq ($(SPMATH),1)
+        CFLAGS+=-DWOLFSSL_SP_ASM -DWOLFSSL_SP_ARM_CORTEX_M_ASM
+        MATH_OBJS += ./lib/wolfssl/wolfcrypt/src/sp_cortexm.o
+      endif
+    endif
+  endif
+endif
+
+## RISCV
+ifeq ($(ARCH),RISCV)
+  CROSS_COMPILE:=riscv32-unknown-elf-
+  CFLAGS+=-fno-builtin-printf -DUSE_PLIC -DUSE_M_TIME -g -march=rv32imac -mabi=ilp32 -mcmodel=medany -nostartfiles -DARCH_RISCV
+  LDFLAGS+=-march=rv32imac -mabi=ilp32 -mcmodel=medany
+  OBJS+=src/boot_riscv.o src/vector_riscv.o
+  ARCH_FLASH_OFFSET=0x20400000
+endif
+
+## Toolchain setup
+CC=$(CROSS_COMPILE)gcc
+LD=$(CROSS_COMPILE)gcc
+AS=$(CROSS_COMPILE)gcc
+OBJCOPY:=$(CROSS_COMPILE)objcopy
+SIZE:=$(CROSS_COMPILE)size
+BOOT_IMG?=test-app/image.bin
+
+## Target specific configuration
+ifeq ($(TARGET),samr21)
+  CORTEX_M0=1
+endif
+
+ifeq ($(TARGET),kinetis)
+  CFLAGS+= -I$(KINETIS_DRIVERS)/drivers -I$(KINETIS_DRIVERS) -DCPU_$(KINETIS_CPU) -I$(KINETIS_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1
+  OBJS+= $(KINETIS_DRIVERS)/drivers/fsl_clock.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_flash.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_cache.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_controller.o
+  ## The following lines can be used to enable HW acceleration
+  ##ifeq ($(KINETIS_CPU),MK82FN256VLL15)
+  ##  ECC_EXTRA_CFLAGS+=-DFREESCALE_LTC_ECC -DFREESCALE_USE_LTC
+  ##  ECC_EXTRA_OBJS+=./lib/wolfssl/wolfcrypt/src/port/nxp/ksdk_port.o $(KINETIS_DRIVERS)/drivers/fsl_ltc.o
+  ##endif
+endif
diff --git a/hal/hifive1.c b/hal/hifive1.c
new file mode 100644
index 0000000000..af0a75121d
--- /dev/null
+++ b/hal/hifive1.c
@@ -0,0 +1,61 @@
+/* hifive1.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdint.h>
+#include <target.h>
+#ifndef ARCH_RISCV
+#   error "wolfBoot hifive1 HAL: wrong architecture selected. Please compile with ARCH=RISCV."
+#endif
+
+#ifdef __WOLFBOOT
+
+void hal_init(void)
+{
+}
+
+void hal_prepare_boot(void)
+{
+}
+
+#endif
+
+int hal_flash_write(uint32_t address, const uint8_t *data, int len)
+{
+    return 0;
+}
+
+void hal_flash_unlock(void)
+{
+}
+
+void hal_flash_lock(void)
+{
+}
+
+
+int hal_flash_erase(uint32_t address, int len)
+{
+    return 0;
+}
+
+
+
+
diff --git a/hal/hifive1.ld b/hal/hifive1.ld
new file mode 100644
index 0000000000..4db313e03f
--- /dev/null
+++ b/hal/hifive1.ld
@@ -0,0 +1,52 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _reset )
+
+MEMORY
+{
+  FLASH(rxai!w) : ORIGIN = 0x20400000, LENGTH = 512K
+  RAM(wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+SECTIONS
+{
+    .text :
+    {
+        _start_text = .;
+        KEEP(*(.init))
+        . = ORIGIN(FLASH) + 0x100;
+        _start_vector = .;
+        KEEP(*(.isr_vector))
+        *(.text*)
+        *(.rodata*)
+        . = ALIGN(4);
+        _end_text = .;
+    } > FLASH
+
+    _stored_data = .;
+
+    .data : AT (_stored_data)
+    {
+        . = ALIGN(4096);
+        _start_data = .;
+        *(.data*)
+        _global_pointer = . + 0x800;
+        *(.sdata*)
+        . = ALIGN(4);
+        _end_data = .;
+    } > RAM
+
+    .bss :
+    {
+        _start_bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _end_bss = .;
+        _end = .;
+    } > RAM
+
+}
+
+PROVIDE(_start_heap = _end);
+PROVIDE(_end_stack  = ORIGIN(RAM) + (LENGTH(RAM)) );
diff --git a/hal/kinetis.c b/hal/kinetis.c
index 184e8f86b8..5c0beea09a 100644
--- a/hal/kinetis.c
+++ b/hal/kinetis.c
@@ -35,7 +35,6 @@ static int flash_init = 0;
 #endif
 
 #ifdef __WOLFBOOT
-#define CPU_CORE_CLOCK             120000000U
 
 static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
 {
@@ -44,6 +43,13 @@ static void CLOCK_CONFIG_SetFllExtRefDiv(uint8_t frdiv)
 
 static void do_flash_init(void);
 
+/* Assert hook needed by Kinetis SDK */
+void __assert_func(const char *a, int b, const char *c, const char *d)
+{
+    while(1)
+        ;
+}
+
 /* This are the registers for the NV flash configuration area.
  * Access these field by setting the relative flags in NV_Flash_Config.
  */
@@ -68,13 +74,51 @@ const uint8_t __attribute__((section(".flash_config"))) NV_Flash_Config[NVTYPE_L
     0xFF
 };
 
-
-/* Assert hook needed by Kinetis SDK */
-void __assert_func(const char *a, int b, const char *c, const char *d)
+#if defined(CPU_MK82FN256VLL15)
+struct stage1_config
 {
-    while(1)
-        ;
-}
+    uint32_t tag;               
+    uint32_t crcStartAddress;   
+    uint32_t crcByteCount;      
+    uint32_t crcExpectedValue;  
+    uint8_t  enabledPeripherals; 
+    uint8_t  i2cSlaveAddress;    
+    uint16_t peripheralDetectionTimeoutMs; 
+    uint16_t usbVid; 
+    uint16_t usbPid; 
+    uint32_t usbStringsPointer; 
+    uint8_t  clockFlags;   
+    uint8_t  clockDivider; 
+    uint8_t  bootFlags; 
+    uint8_t  RESERVED1;
+    uint32_t mmcauConfigPointer; 
+    uint32_t keyBlobPointer;     
+    uint8_t  RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; 
+    uint8_t  RESERVED3[12];
+};
+
+const struct stage1_config __attribute__((section(".stage1_config"))) 
+ NV_Stage1_Config = {
+    .tag = 0x6766636BU,                      /* Magic Number */
+    .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+    .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+    .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+    .enabledPeripherals = 0x17,              /* Enable all peripherals */
+    .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+    .peripheralDetectionTimeoutMs = 0x01F4U, /* Use default timeout */
+    .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+    .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+    .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+    .clockFlags = 0x01,                      /* Enable High speed mode */
+    .clockDivider = 0xFF,                    /* Use clock divider 1 */
+    .bootFlags = 0x01,                       /* Enable communication with host */
+    .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+    .keyBlobPointer = 0x000001000,           /* keyblob data is at 0x1000 */
+    .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+};
+#endif
+
 
 #define MCG_PLL_DISABLE                                   0U  /*!< MCGPLLCLK disabled */
 #define OSC_CAP0P                                         0U  /*!< Oscillator 0pF capacitor load */
@@ -82,6 +126,10 @@ void __assert_func(const char *a, int b, const char *c, const char *d)
 #define SIM_OSC32KSEL_RTC32KCLK_CLK                       2U  /*!< OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
 #define SIM_PLLFLLSEL_IRC48MCLK_CLK                       3U  /*!< PLLFLL select: IRC48MCLK clock */
 #define SIM_PLLFLLSEL_MCGPLLCLK_CLK                       1U  /*!< PLLFLL select: MCGPLLCLK clock */
+#define SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV 1U    /*!< SIM CLKDIV1 maximum run mode core/system divider configurations */
+#define SIM_CLKDIV1_RUN_MODE_MAX_BUS_DIV 3U     /*!< SIM CLKDIV1 maximum run mode bus divider configurations */
+#define SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV 3U /*!< SIM CLKDIV1 maximum run mode flexbus divider configurations */
+#define SIM_CLKDIV1_RUN_MODE_MAX_FLASH_DIV 7U   /*!< SIM CLKDIV1 maximum run mode flash divider configurations */
 
 static void CLOCK_CONFIG_FllStableDelay(void)
 {
@@ -92,7 +140,6 @@ static void CLOCK_CONFIG_FllStableDelay(void)
     }
 }
 
-/* Clock configuration for K64F */
 const mcg_config_t mcgConfig_BOARD_BootClockRUN =
 {
     .mcgMode = kMCG_ModePEE,                  /* PEE - PLL Engaged External */
@@ -103,19 +150,34 @@ const mcg_config_t mcgConfig_BOARD_BootClockRUN =
     .drs = kMCG_DrsLow,                       /* Low frequency range */
     .dmx32 = kMCG_Dmx32Default,               /* DCO has a default range of 25% */
     .oscsel = kMCG_OscselOsc,                 /* Selects System Oscillator (OSCCLK) */
+#if defined(CPU_MK64FN1M0VLL12)
     .pll0Config =
     {
         .enableMode = MCG_PLL_DISABLE,    /* MCGPLLCLK disabled */
         .prdiv = 0x13U,                   /* PLL Reference divider: divided by 20 */
         .vdiv = 0x18U,                    /* VCO divider: multiplied by 48 */
     },
+#elif defined(CPU_MK82FN256VLL15)
+    .pll0Config =
+    {
+        .enableMode = MCG_PLL_DISABLE, /* MCGPLLCLK disabled */
+        .prdiv = 0x0U,                 /* PLL Reference divider: divided by 1 */
+        .vdiv = 0x9U,                  /* VCO divider: multiplied by 25 */
+    },
+#else
+#       error("The selected Kinetis MPU does not have a clock line configuration. Please edit hal/kinetis.c")
+#endif
+
 };
+
+#if defined(CPU_MK64FN1M0VLL12)
 const sim_clock_config_t simConfig_BOARD_BootClockRUN =
 {
     .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
     .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
     .clkdiv1 = 0x1240000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /3, OUTDIV4: /5 */
 };
+
 const osc_config_t oscConfig_BOARD_BootClockRUN =
 {
     .freq = 50000000U,                        /* Oscillator frequency: 50000000Hz */
@@ -127,13 +189,41 @@ const osc_config_t oscConfig_BOARD_BootClockRUN =
     }
 };
 
+#elif defined(CPU_MK82FN256VLL15)
+
+const sim_clock_config_t simConfig_BOARD_BootClockRUN = {
+    .pllFllSel = SIM_PLLFLLSEL_MCGPLLCLK_CLK, /* PLLFLL select: MCGPLLCLK clock */
+    .pllFllDiv = 0,                           /* PLLFLLSEL clock divider divisor: divided by 1 */
+    .pllFllFrac = 0,                          /* PLLFLLSEL clock divider fraction: multiplied by 1 */
+    .er32kSrc = SIM_OSC32KSEL_RTC32KCLK_CLK,  /* OSC32KSEL select: RTC32KCLK clock (32.768kHz) */
+    .clkdiv1 = 0x1150000U,                    /* SIM_CLKDIV1 - OUTDIV1: /1, OUTDIV2: /2, OUTDIV3: /2, OUTDIV4: /6 */
+};
+
+const osc_config_t oscConfig_BOARD_BootClockRUN = {
+    .freq = 12000000U,                /* Oscillator frequency: 12000000Hz */
+    .capLoad = (OSC_CAP0P),           /* Oscillator capacity load: 0pF */
+    .workMode = kOSC_ModeOscLowPower, /* Oscillator low power */
+    .oscerConfig = {
+        .enableMode =
+            kOSC_ErClkEnable, /* Enable external reference clock, disable external reference clock in STOP mode */
+        .erclkDiv = 0,        /* Divider for OSCERCLK: divided by 1 */
+    }
+};
+#endif
+
+
 void hal_init(void)
 {
     /* Disable MPU */
     SYSMPU_Enable(SYSMPU, false);
 
     /* Set the system clock dividers in SIM to safe value. */
+#if defined(CPU_MK64FN1M0VLL12)
     CLOCK_SetSimSafeDivs();
+#elif defined(CPU_MK82FN256VLL15)
+    CLOCK_SetOutDiv(SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV, SIM_CLKDIV1_RUN_MODE_MAX_BUS_DIV,
+                    SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV, SIM_CLKDIV1_RUN_MODE_MAX_FLASH_DIV);
+#endif
     /* Initializes OSC0 according to board configuration. */
     CLOCK_InitOsc0(&oscConfig_BOARD_BootClockRUN);
     CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockRUN.freq);
@@ -151,6 +241,45 @@ void hal_init(void)
     CLOCK_SetSimConfig(&simConfig_BOARD_BootClockRUN);
     do_flash_init();
 }
+#if 0
+void BOARD_BootClockHSRUN(void)
+{
+    /* In HSRUN mode, the maximum allowable change in frequency of the system/bus/core/flash is
+    * restricted to x2, to follow this restriction, enter HSRUN mode should follow:
+ * 1.set CLKDIV1 to safe divider value.
+    * 2.set the PLL or FLL output target frequency for HSRUN mode.
+    * 3.switch to HSRUN mode.
+    * 4.switch to HSRUN mode target requency value.
+    */
+
+    /* Set the system clock dividers in SIM to safe value. */
+    CLOCK_SetOutDiv(SIM_CLKDIV1_RUN_MODE_MAX_CORE_DIV, SIM_CLKDIV1_RUN_MODE_MAX_BUS_DIV,
+                    SIM_CLKDIV1_RUN_MODE_MAX_FLEXBUS_DIV, SIM_CLKDIV1_RUN_MODE_MAX_FLASH_DIV);
+    /* Initializes OSC0 according to board configuration. */
+    CLOCK_InitOsc0(&oscConfig_BOARD_BootClockHSRUN);
+    CLOCK_SetXtal0Freq(oscConfig_BOARD_BootClockHSRUN.freq);
+    /* Configure the Internal Reference clock (MCGIRCLK). */
+    CLOCK_SetInternalRefClkConfig(mcgConfig_BOARD_BootClockHSRUN.irclkEnableMode, mcgConfig_BOARD_BootClockHSRUN.ircs,
+                                  mcgConfig_BOARD_BootClockHSRUN.fcrdiv);
+    /* Configure FLL external reference divider (FRDIV). */
+    CLOCK_CONFIG_SetFllExtRefDiv(mcgConfig_BOARD_BootClockHSRUN.frdiv);
+    /* Set MCG to PEE mode. */
+    CLOCK_BootToPeeMode(mcgConfig_BOARD_BootClockHSRUN.oscsel, kMCG_PllClkSelPll0,
+                        &mcgConfig_BOARD_BootClockHSRUN.pll0Config);
+
+    /* Set HSRUN power mode */
+    SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
+    SMC_SetPowerModeHsrun(SMC);
+    while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
+    {
+    }
+
+    /* Set the clock configuration in SIM module. */
+    CLOCK_SetSimConfig(&simConfig_BOARD_BootClockHSRUN);
+    /* Set SystemCoreClock variable. */
+    SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
+}
+#endif
 
 void hal_prepare_boot(void)
 {
diff --git a/hal/kinetis.ld b/hal/kinetis.ld
index 4829e75de7..0abb26fc37 100644
--- a/hal/kinetis.ld
+++ b/hal/kinetis.ld
@@ -11,6 +11,8 @@ SECTIONS
     {
         _start_text = .;
         KEEP(*(.isr_vector))
+        . = 0x3c0;
+        KEEP(*(.stage1_config))
         . = 0x400;
         KEEP(*(.flash_config))
         . = ALIGN(8);
diff --git a/include/target.h b/include/target.h
index 658f599e96..a9b3ec6dea 100644
--- a/include/target.h
+++ b/include/target.h
@@ -6,7 +6,6 @@
  * Ensure that your firmware entry point is
  * at FLASH_AREA_IMAGE_0_OFFSET + 0x100
  */
-
 #   define WOLFBOOT_SECTOR_SIZE			        0x20000
 #   define WOLFBOOT_PARTITION_BOOT_ADDRESS      0x20000
 
@@ -27,4 +26,4 @@
 #   define WOLFBOOT_PARTITION_SWAP_ADDRESS      0x60000
 #endif
 
-#endif
+#endif /* H_TARGETS_TARGET_ */
diff --git a/include/user_settings.h b/include/user_settings.h
index 0201547b9d..72f9b01830 100644
--- a/include/user_settings.h
+++ b/include/user_settings.h
@@ -44,6 +44,7 @@
 #   define USE_FAST_MATH
 #   define WOLFSSL_SHA512
 #   define NO_ASN
+#   define NO_BIG_INT
 #endif
 
 #ifdef WOLFBOOT_SIGN_ECC256
@@ -53,12 +54,19 @@
 #   define ECC_ALT_SIZE
 #   define NO_ECC_SIGN
 #   define NO_ECC_EXPORT
-#   define USE_FAST_MATH
 #   define WOLFSSL_SHA512
+# ifdef FREESCALE_USE_LTC
+#   define LTC_MAX_ECC_BITS (256)
+#   define LTC_MAX_INT_BYTES (128)
+#   define LTC_BASE ((LTC_Type *)LTC0_BASE)
+# else
+#   define NO_BIG_INT
+#   define USE_FAST_MATH
 #   define WOLFSSL_SP_SMALL
 #   define SP_WORD_SIZE 32
 #   define WOLFSSL_HAVE_SP_ECC
 #   define WOLFSSL_SP_MATH
+# endif
 #   define NO_ASN
 //#   define NO_ECC_SIGN
 #   define NO_ECC_DHE
@@ -69,5 +77,4 @@
 #	define NO_AES
 #	define NO_CMAC
 #	define NO_CODING
-#   define NO_BIG_INT
 #	define NO_RSA
diff --git a/lib/wolfssl b/lib/wolfssl
index b528997d30..e4059a65b9 160000
--- a/lib/wolfssl
+++ b/lib/wolfssl
@@ -1 +1 @@
-Subproject commit b528997d30fab68fa64f4c49314f8275e77fd948
+Subproject commit e4059a65b9b53ea2817b81afe6a0562ad6a5d342
diff --git a/src/wolfboot.c b/src/boot_arm.c
similarity index 99%
rename from src/wolfboot.c
rename to src/boot_arm.c
index 398f73a67d..de1ab6a717 100644
--- a/src/wolfboot.c
+++ b/src/boot_arm.c
@@ -1,4 +1,4 @@
-/* wolfboot.c
+/* boot_arm.c 
  *
  * Copyright (C) 2018 wolfSSL Inc.
  *
@@ -109,7 +109,6 @@ void do_boot(const uint32_t *app_offset)
     asm volatile("mov pc, %0" ::"r"(app_entry));
 }
 
-
 __attribute__ ((section(".isr_vector")))
 void (* const IV[])(void) =
 {
diff --git a/src/boot_riscv.c b/src/boot_riscv.c
new file mode 100644
index 0000000000..e1b8379532
--- /dev/null
+++ b/src/boot_riscv.c
@@ -0,0 +1,86 @@
+/* boot_riscv.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdint.h>
+
+extern void trap_entry(void);
+extern void trap_exit(void);
+
+extern uint32_t  _start_vector;
+extern uint32_t  _stored_data;
+extern uint32_t  _start_data;
+extern uint32_t  _end_data;
+extern uint32_t  _start_bss;
+extern uint32_t  _end_bss;
+extern uint32_t  _end_stack;
+extern uint32_t  _start_heap;
+extern uint32_t  _global_pointer;
+extern void (* const IV[])(void);
+
+extern void main(void);
+void __attribute__((naked,section(".init"))) _reset(void) {
+    register uint32_t *src, *dst;
+    asm volatile("la gp, _global_pointer");
+    asm volatile("la sp, _end_stack");
+
+    /* Set up vectored interrupt, with IV starting at offset 0x100 */
+    asm volatile("csrw mtvec, %0":: "r"((uint8_t *)(&_start_vector) + 1));
+
+    src = (uint32_t *) &_stored_data;
+    dst = (uint32_t *) &_start_data;
+    /* Copy the .data section from flash to RAM. */
+    while (dst < (uint32_t *)&_end_data) {
+        *dst = *src;
+        dst++;
+        src++;
+    }
+
+    /* Initialize the BSS section to 0 */
+    dst = &_start_bss;
+    while (dst < (uint32_t *)&_end_bss) {
+        *dst = 0U;
+        dst++;
+    }
+
+    /* Run wolfboot */
+    main();
+    while(1)
+        ;
+}
+
+void do_boot(const uint32_t *app_offset)
+{
+
+}
+
+static uint32_t synctrap_cause = 0;
+void __attribute__((naked)) isr_synctrap(void)
+{
+    asm volatile("csrr %0,mcause" : "=r"(synctrap_cause));
+    //asm volatile("ebreak");
+}
+
+void isr_empty(void)
+{
+
+}
+
+
diff --git a/src/vector_riscv.S b/src/vector_riscv.S
new file mode 100644
index 0000000000..4212b3873e
--- /dev/null
+++ b/src/vector_riscv.S
@@ -0,0 +1,141 @@
+/**
+ * RISC-V bootup
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+.macro trap_entry
+    addi sp, sp, -64
+    sw x1,  0(sp)
+    sw x5,  4(sp)
+    sw x6,  8(sp)
+    sw x7,  12(sp)
+    sw x10, 16(sp)
+    sw x11, 20(sp)
+    sw x12, 24(sp)
+    sw x13, 28(sp)
+    sw x14, 32(sp)
+    sw x15, 36(sp)
+    sw x16, 40(sp)
+    sw x17, 44(sp)
+    sw x28, 48(sp)
+    sw x29, 52(sp)
+    sw x30, 56(sp)
+    sw x31, 60(sp)
+.endm
+
+
+.macro trap_exit
+  lw x1,  0(sp)
+  lw x5,  4(sp)
+  lw x6,  8(sp)
+  lw x7,  12(sp)
+  lw x10, 16(sp)
+  lw x11, 20(sp)
+  lw x12, 24(sp)
+  lw x13, 28(sp)
+  lw x14, 32(sp)
+  lw x15, 36(sp)
+  lw x16, 40(sp)
+  lw x17, 44(sp)
+  lw x28, 48(sp)
+  lw x29, 52(sp)
+  lw x30, 56(sp)
+  lw x31, 60(sp)
+  addi sp, sp, 64
+  mret
+.endm
+
+.section .isr_vector
+.align 8
+
+.global IV
+
+IV:
+    j _synctrap
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+
+_synctrap:
+  trap_entry
+  jal isr_synctrap
+  trap_exit
+
+trap_empty:
+    nop
diff --git a/test-app/app.ld b/test-app/ARM.ld
similarity index 92%
rename from test-app/app.ld
rename to test-app/ARM.ld
index 9fd8290037..8236aafdbe 100644
--- a/test-app/app.ld
+++ b/test-app/ARM.ld
@@ -1,6 +1,6 @@
 MEMORY
 {
-    FLASH (rx) : ORIGIN = 0x00020100, LENGTH = 0x001FF00
+    FLASH (rx) : ORIGIN = 0x0020100, LENGTH = 0x001FF00
     RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00010000
 }
 
diff --git a/test-app/Makefile b/test-app/Makefile
index 4eef45e1be..de93724e1f 100644
--- a/test-app/Makefile
+++ b/test-app/Makefile
@@ -1,11 +1,25 @@
-CROSS_COMPILE:=arm-none-eabi-
-CC:=$(CROSS_COMPILE)gcc
-LD:=$(CROSS_COMPILE)gcc
-OBJS:=startup.o main.o timer.o led.o system.o ../src/libwolfboot.o ../hal/$(TARGET).o
 TARGET?=none
-LSCRIPT:=app.ld
-OBJCOPY:=$(CROSS_COMPILE)objcopy
-CFLAGS:=-mcpu=cortex-m3 -mthumb -g -ggdb -Wall -Wno-main -Wstack-usage=200 -ffreestanding -Wno-unused -DPLATFORM_$(TARGET) -I../include -nostartfiles
+ARCH?=ARM
+KINETIS_CMSIS?=$(KINETIS)/CMSIS
+
+CFLAGS:=-g -ggdb -Wall -Wstack-usage=200 -ffreestanding -Wno-unused -DPLATFORM_$(TARGET) -I../include -nostartfiles
+
+APP_OBJS:=$(TARGET).o led.o system.o timer.o ../hal/$(TARGET).o ../src/libwolfboot.o
+include ../arch.mk
+
+ifeq ($(ARCH),RISCV)
+  APP_OBJS+=startup_riscv.o vector_riscv.o
+endif
+
+ifeq ($(ARCH),ARM)
+  APP_OBJS+=startup_arm.o
+endif
+
+ifeq ($(V),0)
+  Q=@
+endif
+
+LSCRIPT:=$(ARCH).ld
 LDFLAGS:=$(CFLAGS) -T $(LSCRIPT) -Wl,-gc-sections -Wl,-Map=image.map
 
 ifeq ($(EXT_FLASH),1)
@@ -14,24 +28,65 @@ endif
 
 ifeq ($(SPI_FLASH),1)
   CFLAGS+=-DSPI_FLASH
-  OBJS+=../hal/spi/spi_drv_$(TARGET).o ../src/spi_flash.o
+  APP_OBJS+=../hal/spi/spi_drv_$(TARGET).o ../src/spi_flash.o
 endif
 
-image.bin: image.elf
-	$(OBJCOPY) -O binary $^ $@
+ifeq ($(TARGET),kinetis)
+  CFLAGS+= -I$(KINETIS_DRIVERS)/drivers -I$(KINETIS_DRIVERS) -DCPU_$(KINETIS_CPU) -I$(KINETIS_CMSIS)/Include -DDEBUG_CONSOLE_ASSERT_DISABLE=1 -DNVM_FLASH_WRITEONCE=1
+  APP_OBJS+= $(KINETIS_DRIVERS)/drivers/fsl_clock.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_flash.o $(KINETIS_DRIVERS)/drivers/fsl_ftfx_cache.o \
+		 $(KINETIS_DRIVERS)/drivers/fsl_ftfx_controller.o $(KINETIS_DRIVERS)/drivers/fsl_gpio.o
+endif
+
+ifeq ($(TARGET),hifive1)
+  CFLAGS+=-I$(FREEDOM_E_SDK)/freedom-metal/ -D__METAL_MACHINE_HEADER=\"$(FREEDOM_E_SDK)/bsp/sifive-hifive1/metal.h\"
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/clock.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/led.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/cache.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/cpu.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/gpio.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/interrupt.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/uart.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/tty.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/spi.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/shutdown.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/timer.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,fe310-g000,hfrosc.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,fe310-g000,hfxosc.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,fe310-g000,pll.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,fe310-g000,prci.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,spi0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,uart0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,global-external-interrupts0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,local-external-interrupts0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,gpio0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/sifive,gpio-leds.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/riscv,clint0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/riscv,plic0.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/riscv,cpu.o
+  APP_OBJS+=$(FREEDOM_E_SDK)/freedom-metal/src/drivers/fixed-clock.o
+endif
+
+standalone:CFLAGS+=-DTEST_APP_STANDALONE
+standalone:LDFLAGS:=$(CFLAGS) -T standalone.ld -Wl,-gc-sections -Wl,-Map=image.map
 
-image.elf: $(OBJS) $(LSCRIPT)
-	$(LD) $(LDFLAGS) $(OBJS) -o $@
+image.bin: image.elf
+	@echo "\t[BIN] $@"
+	$(Q)$(OBJCOPY) -O binary $^ $@
 
-standalone:CFLAGS+=-DPLATFORM_stm32f4
-standalone:LDFLAGS:=-T standalone.ld -Wl,-gc-sections -Wl,-Map=image.map -nostdlib
+image.elf: $(APP_OBJS) $(LSCRIPT)
+	@echo "\t[LD] $@"
+	$(Q)$(LD) $(LDFLAGS) $(APP_OBJS) -o $@
 
 
 standalone: image.bin
-	
-startup.o: startup.c
 
-main.o: main.c
+%.o:%.c
+	@echo "\t[CC-$(ARCH)] $@"
+	$(Q)$(CC) $(CFLAGS) -c -o $@ $^
+
+%.o:%.S
+	@echo "\t[AS-$(ARCH)] $@"
+	$(Q)$(CC) $(CFLAGS) -c -o $@ $^
 
 clean:
-	rm -f image.bin* image.elf *.o image.map tags
+	@rm -f image.bin* image.elf *.o image.map tags
diff --git a/test-app/RISCV.ld b/test-app/RISCV.ld
new file mode 100644
index 0000000000..6f20117bc8
--- /dev/null
+++ b/test-app/RISCV.ld
@@ -0,0 +1,53 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _reset )
+
+MEMORY
+{
+  FLASH(rxai!w) : ORIGIN = 0x20404100, LENGTH = (512K - 0x4100)
+  RAM(wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K
+}
+
+SECTIONS
+{
+    .text :
+    {
+        _start_text = .;
+        KEEP(*(.init))
+        . = ORIGIN(FLASH) + 0x100;
+        _start_vector = .;
+        KEEP(*(.isr_vector))
+        *(.text*)
+        *(.rodata*)
+        *(.srodata*)
+        . = ALIGN(4);
+        _end_text = .;
+    } > FLASH
+
+    _stored_data = .;
+
+    .data : AT (_stored_data)
+    {
+        . = ALIGN(4096);
+        _start_data = .;
+        *(.data*)
+        _global_pointer = . + 0x800;
+        *(.sdata*)
+        . = ALIGN(4);
+        _end_data = .;
+    } > RAM
+
+    .bss :
+    {
+        _start_bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        _end_bss = .;
+        _end = .;
+    } > RAM
+
+}
+
+PROVIDE(_start_heap = _end);
+PROVIDE(_end_stack  = ORIGIN(RAM) + (LENGTH(RAM)) );
diff --git a/test-app/hifive1.c b/test-app/hifive1.c
new file mode 100644
index 0000000000..7c6b0ad276
--- /dev/null
+++ b/test-app/hifive1.c
@@ -0,0 +1,32 @@
+/* hifive1.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "hal.h"
+#include "wolfboot/wolfboot.h"
+
+void main(void) {
+    while(1)
+        ;
+}
+
diff --git a/test-app/kinetis.c b/test-app/kinetis.c
new file mode 100644
index 0000000000..75cbe8f7f2
--- /dev/null
+++ b/test-app/kinetis.c
@@ -0,0 +1,149 @@
+/* main.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "fsl_common.h"
+#include "fsl_port.h"
+#include "fsl_gpio.h"
+#include "fsl_clock.h"
+#include "wolfboot/wolfboot.h"
+
+/* FRDM-K64 board */
+#if defined(CPU_MK64FN1M0VLL12)
+#define BOARD_LED_GPIO GPIOB
+#define BOARD_LED_GPIO_PORT PORTB
+#define BOARD_LED_GPIO_CLOCK kCLOCK_PortB
+#define BOARD_LED_GPIO_PIN 23U
+/* FRDM-K82 board */
+#elif defined (CPU_MK82FN256VLL15)
+#define BOARD_LED_GPIO_PORT PORTC
+#define BOARD_LED_GPIO_CLOCK kCLOCK_PortC
+#define BOARD_LED_GPIO GPIOC
+#define BOARD_LED_GPIO_PIN 8U
+#endif
+
+#ifdef TEST_APP_STANDALONE
+/* This are the registers for the NV flash configuration area.
+ * Access these field by setting the relative flags in NV_Flash_Config.
+ */
+#define NVTYPE_LEN (16) 
+
+const uint8_t __attribute__((section(".flash_config"))) NV_Flash_Config[NVTYPE_LEN] = {
+    /* Backdoor comparison key (2 words) */
+    0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
+
+    /* P-Flash protection 1 */
+    0xFF, 0xFF,
+    /* P-Flash protection 2 */
+    0xFF, 0xFF,
+
+    /* Flash security register */
+    ((0xFE)),
+    /* Flash option register */
+    0xFF,
+    /* EERAM protection register */
+    0xFF,
+    /* D-Flash protection register */
+    0xFF
+};
+
+#if defined(CPU_MK82FN256VLL15)
+struct stage1_config
+{
+    uint32_t tag;               
+    uint32_t crcStartAddress;   
+    uint32_t crcByteCount;      
+    uint32_t crcExpectedValue;  
+    uint8_t  enabledPeripherals; 
+    uint8_t  i2cSlaveAddress;    
+    uint16_t peripheralDetectionTimeoutMs; 
+    uint16_t usbVid; 
+    uint16_t usbPid; 
+    uint32_t usbStringsPointer; 
+    uint8_t  clockFlags;   
+    uint8_t  clockDivider; 
+    uint8_t  bootFlags; 
+    uint8_t  RESERVED1;
+    uint32_t mmcauConfigPointer; 
+    uint32_t keyBlobPointer;     
+    uint8_t  RESERVED2[8];
+    uint32_t qspiConfigBlockPtr; 
+    uint8_t  RESERVED3[12];
+};
+
+const struct stage1_config __attribute__((section(".stage1_config"))) 
+ NV_Stage1_Config = {
+    .tag = 0x6766636BU,                      /* Magic Number */
+    .crcStartAddress = 0xFFFFFFFFU,          /* Disable CRC check */
+    .crcByteCount = 0xFFFFFFFFU,             /* Disable CRC check */
+    .crcExpectedValue = 0xFFFFFFFFU,         /* Disable CRC check */
+    .enabledPeripherals = 0x17,              /* Enable all peripherals */
+    .i2cSlaveAddress = 0xFF,                 /* Use default I2C address */
+    .peripheralDetectionTimeoutMs = 0x01F4U, /* Use default timeout */
+    .usbVid = 0xFFFFU,                       /* Use default USB Vendor ID */
+    .usbPid = 0xFFFFU,                       /* Use default USB Product ID */
+    .usbStringsPointer = 0xFFFFFFFFU,        /* Use default USB Strings */
+    .clockFlags = 0x01,                      /* Enable High speed mode */
+    .clockDivider = 0xFF,                    /* Use clock divider 1 */
+    .bootFlags = 0x01,                       /* Enable communication with host */
+    .mmcauConfigPointer = 0xFFFFFFFFU,       /* No MMCAU configuration */
+    .keyBlobPointer = 0x000001000,           /* keyblob data is at 0x1000 */
+    .qspiConfigBlockPtr = 0xFFFFFFFFU        /* No QSPI configuration */
+};
+#endif
+#endif
+
+
+
+void main(void) {
+    int i = 0;
+#ifdef CPU_MK64FN1M0VLL12
+    /* Immediately disable Watchdog after boot */
+    /*  Write Keys to unlock register */
+    *((volatile unsigned short *)0x4005200E) = 0xC520;
+    *((volatile unsigned short *)0x4005200E) = 0xD928;
+    /* disable watchdog via STCTRLH register */
+    *((volatile unsigned short *)0x40052000) = 0x01D2u;
+#endif
+    gpio_pin_config_t led_config = {
+        kGPIO_DigitalOutput, 0,
+    };
+
+    CLOCK_EnableClock(BOARD_LED_GPIO_CLOCK);
+    PORT_SetPinMux(BOARD_LED_GPIO_PORT, BOARD_LED_GPIO_PIN, kPORT_MuxAsGpio);
+    GPIO_PinWrite(BOARD_LED_GPIO, BOARD_LED_GPIO_PIN, led_config.outputLogic);
+    BOARD_LED_GPIO->PDDR |= (1U << BOARD_LED_GPIO_PIN);
+    GPIO_PortClear(BOARD_LED_GPIO, 1u << BOARD_LED_GPIO_PIN);
+
+    while(1) {
+        for(i = 0; i < 7200000; i++) {
+
+        }
+
+        GPIO_PortToggle(BOARD_LED_GPIO, 1 << BOARD_LED_GPIO_PIN);
+    }
+
+    while(1)
+        __WFI();
+}
+
diff --git a/test-app/led.c b/test-app/led.c
index bfe66e1634..476098b40e 100644
--- a/test-app/led.c
+++ b/test-app/led.c
@@ -21,6 +21,7 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
 
+#ifdef PLATFORM_stm32f4
 #include <stdint.h>
 #include "wolfboot/wolfboot.h"
 
@@ -69,3 +70,4 @@ void boot_led_on(void)
     GPIOD_BSRR |= (1 << pin);
 }
 
+#endif /** PLATFORM_stm32f4 **/
diff --git a/test-app/nrf52.c b/test-app/nrf52.c
new file mode 100644
index 0000000000..6d2ab26f35
--- /dev/null
+++ b/test-app/nrf52.c
@@ -0,0 +1,52 @@
+/* main.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "wolfboot/wolfboot.h"
+
+
+#define GPIO_BASE (0x50000000)
+#define GPIO_OUT        *((volatile uint32_t *)(GPIO_BASE + 0x504))
+#define GPIO_OUTSET     *((volatile uint32_t *)(GPIO_BASE + 0x508))
+#define GPIO_OUTCLR     *((volatile uint32_t *)(GPIO_BASE + 0x50C))
+#define GPIO_PIN_CNF     ((volatile uint32_t *)(GPIO_BASE + 0x700)) // Array
+
+static void gpiotoggle(uint32_t pin)
+{
+    uint32_t reg_val = GPIO_OUT;
+    GPIO_OUTCLR = reg_val & (1 << pin);
+    GPIO_OUTSET = (~reg_val) & (1 << pin);
+}
+
+void main(void)
+{
+    uint32_t pin = 19;
+    int i;
+    GPIO_PIN_CNF[pin] = 1; /* Output */
+    while(1) {
+        gpiotoggle(pin);
+        for (i = 0; i < 800000; i++)  // Wait a bit.
+              asm volatile ("nop");
+    }
+}
+
diff --git a/test-app/samr21.c b/test-app/samr21.c
new file mode 100644
index 0000000000..e0d6792f59
--- /dev/null
+++ b/test-app/samr21.c
@@ -0,0 +1,33 @@
+/* main.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "hal.h"
+#include "wolfboot/wolfboot.h"
+
+void main(void) {
+    asm volatile ("cpsie i");
+    while(1)
+        WFI();
+}
+
diff --git a/test-app/standalone.ld b/test-app/standalone.ld
index beeb24dce9..3deb9753df 100644
--- a/test-app/standalone.ld
+++ b/test-app/standalone.ld
@@ -10,6 +10,11 @@ SECTIONS
     {
         _start_text = .;
         KEEP(*(.isr_vector))
+        . = 0x3c0;
+        KEEP(*(.stage1_config))
+        . = 0x400;
+        KEEP(*(.flash_config))
+        . = ALIGN(8);
         *(.text*)
         *(.rodata*)
         . = ALIGN(4);
diff --git a/test-app/startup.c b/test-app/startup_arm.c
similarity index 100%
rename from test-app/startup.c
rename to test-app/startup_arm.c
diff --git a/test-app/startup_riscv.c b/test-app/startup_riscv.c
new file mode 100644
index 0000000000..e1b8379532
--- /dev/null
+++ b/test-app/startup_riscv.c
@@ -0,0 +1,86 @@
+/* boot_riscv.c
+ *
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ */
+
+#include <stdint.h>
+
+extern void trap_entry(void);
+extern void trap_exit(void);
+
+extern uint32_t  _start_vector;
+extern uint32_t  _stored_data;
+extern uint32_t  _start_data;
+extern uint32_t  _end_data;
+extern uint32_t  _start_bss;
+extern uint32_t  _end_bss;
+extern uint32_t  _end_stack;
+extern uint32_t  _start_heap;
+extern uint32_t  _global_pointer;
+extern void (* const IV[])(void);
+
+extern void main(void);
+void __attribute__((naked,section(".init"))) _reset(void) {
+    register uint32_t *src, *dst;
+    asm volatile("la gp, _global_pointer");
+    asm volatile("la sp, _end_stack");
+
+    /* Set up vectored interrupt, with IV starting at offset 0x100 */
+    asm volatile("csrw mtvec, %0":: "r"((uint8_t *)(&_start_vector) + 1));
+
+    src = (uint32_t *) &_stored_data;
+    dst = (uint32_t *) &_start_data;
+    /* Copy the .data section from flash to RAM. */
+    while (dst < (uint32_t *)&_end_data) {
+        *dst = *src;
+        dst++;
+        src++;
+    }
+
+    /* Initialize the BSS section to 0 */
+    dst = &_start_bss;
+    while (dst < (uint32_t *)&_end_bss) {
+        *dst = 0U;
+        dst++;
+    }
+
+    /* Run wolfboot */
+    main();
+    while(1)
+        ;
+}
+
+void do_boot(const uint32_t *app_offset)
+{
+
+}
+
+static uint32_t synctrap_cause = 0;
+void __attribute__((naked)) isr_synctrap(void)
+{
+    asm volatile("csrr %0,mcause" : "=r"(synctrap_cause));
+    //asm volatile("ebreak");
+}
+
+void isr_empty(void)
+{
+
+}
+
+
diff --git a/test-app/main.c b/test-app/stm32f4.c
similarity index 98%
rename from test-app/main.c
rename to test-app/stm32f4.c
index 7ae59695fe..bd3eb44601 100644
--- a/test-app/main.c
+++ b/test-app/stm32f4.c
@@ -297,7 +297,7 @@ void main(void) {
     while(1)
         ;
 }
-#endif
+#endif /** PLATFROM_stm32f4 **/
 
 #ifdef PLATFORM_nrf52
 #define GPIO_BASE (0x50000000)
@@ -335,3 +335,10 @@ void main(void) {
 }
 #endif
 
+#ifdef PLATFORM_hifive1
+void main(void) {
+    while(1)
+        ;
+}
+#endif
+
diff --git a/test-app/system.c b/test-app/system.c
index b0c9e14a9d..978c354cc8 100644
--- a/test-app/system.c
+++ b/test-app/system.c
@@ -20,7 +20,7 @@
  * along with this program; if not, write to the Free Software
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
-
+#ifdef PLATFORM_stm32f4
 #include <stdint.h>
 #include "system.h"
 
@@ -131,3 +131,4 @@ void clock_config(void)
     RCC_CR &= ~RCC_CR_HSION;
 }
 
+#endif /** PLATFORM_stm32f4 **/
diff --git a/test-app/timer.c b/test-app/timer.c
index 8563b1aed9..bada6faebd 100644
--- a/test-app/timer.c
+++ b/test-app/timer.c
@@ -1,4 +1,4 @@
-/* system.c
+/* timer.c
  *
  * Test bare-metal blinking led application
  *
@@ -21,6 +21,7 @@
  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
  */
 
+#ifdef PLATFORM_stm32f4
 #include <stdint.h>
 #include "system.h"
 #include "led.h"
@@ -161,5 +162,9 @@ void isr_tim2(void)
 
     time_elapsed++;
 }
+#else
+void isr_tim2(void)
+{
+}
 
-
+#endif /** PLATFORM_stm32f4 **/
diff --git a/test-app/vector_riscv.S b/test-app/vector_riscv.S
new file mode 100644
index 0000000000..56ba330f2e
--- /dev/null
+++ b/test-app/vector_riscv.S
@@ -0,0 +1,142 @@
+/**
+ * RISC-V bootup
+ * Copyright (C) 2018 wolfSSL Inc.
+ *
+ * This file is part of wolfBoot.
+ *
+ * wolfBoot is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * wolfBoot is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1335, USA
+ *
+ */
+
+.macro trap_entry
+    addi sp, sp, -64
+    sw x1,  0(sp)
+    sw x5,  4(sp)
+    sw x6,  8(sp)
+    sw x7,  12(sp)
+    sw x10, 16(sp)
+    sw x11, 20(sp)
+    sw x12, 24(sp)
+    sw x13, 28(sp)
+    sw x14, 32(sp)
+    sw x15, 36(sp)
+    sw x16, 40(sp)
+    sw x17, 44(sp)
+    sw x28, 48(sp)
+    sw x29, 52(sp)
+    sw x30, 56(sp)
+    sw x31, 60(sp)
+.endm
+
+
+.macro trap_exit
+  lw x1,  0(sp)
+  lw x5,  4(sp)
+  lw x6,  8(sp)
+  lw x7,  12(sp)
+  lw x10, 16(sp)
+  lw x11, 20(sp)
+  lw x12, 24(sp)
+  lw x13, 28(sp)
+  lw x14, 32(sp)
+  lw x15, 36(sp)
+  lw x16, 40(sp)
+  lw x17, 44(sp)
+  lw x28, 48(sp)
+  lw x29, 52(sp)
+  lw x30, 56(sp)
+  lw x31, 60(sp)
+  addi sp, sp, 64
+  mret
+.endm
+
+.section .isr_vector
+.align 8
+
+.global IV
+
+IV:
+    j _synctrap
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+    j trap_empty
+    .align 2
+
+_synctrap:
+  trap_entry
+  jal isr_synctrap
+  trap_exit
+
+trap_empty:
+    nop