Skip to content
Pro
Block or report user

Report or block wsnyder

Hide content and notifications from this user.

Learn more about blocking users

Contact Support about this user’s behavior.

Learn more about reporting abuse

Report abuse

Organizations

@verilator
Block or report user

Report or block wsnyder

Hide content and notifications from this user.

Learn more about blocking users

Contact Support about this user’s behavior.

Learn more about reporting abuse

Report abuse

Popular repositories

  1. Forked from myhdl/myhdl

    The MyHDL development repository

    Python 1 1

  2. Forked from chipsalliance/Cores-SweRV

    SweRV EH1 core

    SystemVerilog

  3. Forked from SymbiFlow/sv-tests

    Test suite designed to check compliance with the SystemVerilog standard.

    SystemVerilog

  4. Forked from gtkwave/gtkwave

    GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.

    C

  5. Forked from SymbiFlow/conda-packages

    Conda build recipes for the toolchains needed by LiteX / MiSoC firmware

    Shell

735 contributions in the last year

Nov Dec Jan Feb Mar Apr May Jun Jul Aug Sep Oct Nov Mon Wed Fri

Contribution activity

November 2019

Created a pull request in SymbiFlow/sv-tests that received 1 comment

Test fixes

Lots of great tests in this package, thanks. Rather than make a bunch of bugs, here's a combined pull request that fixes several test problems I fo…

+155 −65 1 comment

Created an issue in chipsalliance/Cores-SweRV that received 2 comments

Add test for core & simulator benchmarking

I suggest that the SweRV repo add a "make benchmark", that runs a binary that e.g. runs CoreMark for about 30-60 seconds. Background: I'm using Cor…

2 comments

Seeing something unexpected? Take a look at the GitHub profile guide.

You can’t perform that action at this time.