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CLEARWATER: CP-3989/CP-3940: Add CPUID masking support for Intel Haswell DT and Ivy ... #129

Merged
merged 1 commit into from

3 participants

Rob Hoes xen-git Malcolm Crossley
Rob Hoes
Owner

...Bridge EN and EP

This adds CPU models 0x3c and 0x3e to the whitelist.

Duplicate of #127 for clearwater

Rob Hoes robhoes CP-3989/CP-3940: Add CPUID masking support for Intel Haswell DT and I…
…vy Bridge EN and EP

This adds CPU models 0x3c and 0x3e to the whitelist.

Signed-off-by: Rob Hoes <rob.hoes@citrix.com>
3371545
xen-git
Owner

Can one of the admins verify this patch?

Rob Hoes
Owner

This was accepted/merged to master.

Malcolm Crossley malcolmcrossley merged commit 407dc12 into from
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Commits on Mar 19, 2013
  1. Rob Hoes

    CP-3989/CP-3940: Add CPUID masking support for Intel Haswell DT and I…

    robhoes authored
    …vy Bridge EN and EP
    
    This adds CPU models 0x3c and 0x3e to the whitelist.
    
    Signed-off-by: Rob Hoes <rob.hoes@citrix.com>
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Showing with 2 additions and 1 deletion.
  1. +2 −1  cpuid/cpuid.ml
3  cpuid/cpuid.ml
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@@ -111,7 +111,8 @@ let read_features () =
* It's not sensibly documented, so check by model *)
let has_flexmigration family model stepping =
let fully_maskable_models =
- [0x17l; 0x1dl; 0x1el; 0x1fl; 0x25l; 0x2al; 0x2cl; 0x2cl; 0x2dl; 0x2el; 0x2fl; 0x3al] in
+ [0x17l; 0x1dl; 0x1el; 0x1fl; 0x25l; 0x2al; 0x2cl; 0x2cl; 0x2dl; 0x2el; 0x2fl; 0x3al;
+ 0x3cl; 0x3el] in
if family <> 0x6l then
No
else if model = 0x1dl || (model = 0x17l && stepping >= 4l) then
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