From 714272c6758fb8fe7a6c23d504ba04f5e9db85e5 Mon Sep 17 00:00:00 2001 From: Andrew Date: Fri, 12 Jul 2013 14:22:18 +0100 Subject: [PATCH] refresh of repo to bring it up to date with 13 tools --- app_sdram_benchmark/.cproject | 430 +++++------ app_sdram_benchmark/.project | 2 +- app_sdram_benchmark/Makefile | 5 +- .../src/app_sdram_benchmark.xc | 127 ++-- app_sdram_demo/.cproject | 434 +++++------ app_sdram_demo/.project | 2 +- app_sdram_demo/Makefile | 5 +- app_sdram_demo/src/app_sdram_demo.xc | 18 +- app_sdram_mfg_tests/.cproject | 696 +++++------------- app_sdram_mfg_tests/.project | 16 +- app_sdram_mfg_tests/.xproject | 1 + app_sdram_mfg_tests/Makefile | 5 +- .../src/app_sdram_mfg_tests.xc | 94 +-- app_sdram_regress/.cproject | 440 +++++------ app_sdram_regress/.project | 6 +- app_sdram_regress/Makefile | 5 +- app_sdram_regress/src/app_sdram_regress.xc | 416 ++++++----- doc/api.rst | 1 + doc/examples.rst | 14 +- module_sdram/.cproject | 263 ++++++- .../src/PINOUT_V0/sdram_server_PINOUT_V0.h | 2 +- .../src/PINOUT_V0/sdram_server_PINOUT_V0.xc | 214 +++--- .../sdram_server_PINOUT_V1_IS42S16160D.h | 2 +- .../sdram_server_PINOUT_V1_IS42S16160D.xc | 200 ++--- .../sdram_server_PINOUT_V1_IS42S16400F.h | 2 +- .../sdram_server_PINOUT_V1_IS42S16400F.xc | 52 +- .../sdram_server_PINOUT_V2_IS42S16400F.h | 2 +- .../sdram_server_PINOUT_V2_IS42S16400F.xc | 46 +- module_sdram/src/sdram.h | 32 +- module_sdram/src/sdram_client.xc | 88 +-- module_sdram/src/sdram_commands.h | 3 +- module_sdram/src/sdram_server_common.inc | 57 +- module_sdram_memory_mapper/.cproject | 269 ++++++- .../src/sdram_memory_mapper.h | 12 +- .../src/sdram_memory_mapper.xc | 24 +- xpd.xml | 28 +- 36 files changed, 1922 insertions(+), 2091 deletions(-) create mode 100644 app_sdram_mfg_tests/.xproject diff --git a/app_sdram_benchmark/.cproject b/app_sdram_benchmark/.cproject index f5db0f9..c91793b 100644 --- a/app_sdram_benchmark/.cproject +++ b/app_sdram_benchmark/.cproject @@ -1,10 +1,10 @@ - + - + @@ -16,7 +16,7 @@ xmake - CONFIG=Debug + all true true @@ -24,7 +24,7 @@ xmake - CONFIG=Debug + clean true true @@ -33,13 +33,13 @@ - + - + - + @@ -153,227 +153,173 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Release - all - true - true - true - - - xmake - CONFIG=Release - clean - true - true - true - - - - - - - - - - - - - - - diff --git a/app_sdram_benchmark/.project b/app_sdram_benchmark/.project index 3ae2bda..73c142e 100644 --- a/app_sdram_benchmark/.project +++ b/app_sdram_benchmark/.project @@ -33,7 +33,7 @@ org.eclipse.cdt.make.core.buildArguments - CONFIG=Debug + org.eclipse.cdt.make.core.buildCommand diff --git a/app_sdram_benchmark/Makefile b/app_sdram_benchmark/Makefile index 68d4f9e..2eb03cc 100644 --- a/app_sdram_benchmark/Makefile +++ b/app_sdram_benchmark/Makefile @@ -1,7 +1,7 @@ # The TARGET variable determines what target system the application is # compiled for. It either refers to an XN file in the source directories # or a valid argument for the --target option when compiling -TARGET = SLICEKIT-L2 +TARGET = SLICEKIT-L16 # The APP_NAME variable determines the name of the final .xe file. It should # not include the .xe postfix. If left blank the name will default to @@ -16,8 +16,7 @@ USED_MODULES = module_sdram module_slicekit_support # XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS # If the variable XCC_MAP_FLAGS is set it overrides the flags passed to # xcc for the final link (mapping) stage. -XCC_FLAGS_Debug = -g -O3 -Wcodes -Xmapper -Wcodes -XCC_FLAGS_Release = -g -O3 -Wcodes -Xmapper -Wcodes +XCC_FLAGS = -g -O3 # The VERBOSE variable, if set to 1, enables verbose output from the make system. VERBOSE = 0 diff --git a/app_sdram_benchmark/src/app_sdram_benchmark.xc b/app_sdram_benchmark/src/app_sdram_benchmark.xc index 1970e2a..d6026e6 100644 --- a/app_sdram_benchmark/src/app_sdram_benchmark.xc +++ b/app_sdram_benchmark/src/app_sdram_benchmark.xc @@ -8,20 +8,24 @@ on tile[0]: sdram_ports ports = { XS1_PORT_16A, XS1_PORT_1B, XS1_PORT_1G, XS1_PORT_1C, XS1_PORT_1F, XS1_CLKBLK_1 }; -static float readWords(chanend server, unsigned count, unsigned page_alignment){ +/* + * Plug XA-SK-SDRAM into the STAR slot. Ensure `XMOS LINK` is off. Build and run. + */ + +static float readWords(chanend c_server, unsigned count, unsigned page_alignment){ unsigned buf[SDRAM_ROW_WORDS]; timer t; unsigned now, then; t :> then; for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_buffer_read(server, 0, row, page_alignment, count, buf); - sdram_wait_until_idle(server, buf); + sdram_buffer_read(c_server, 0, row, page_alignment, count, buf); + sdram_wait_until_idle(c_server, buf); } t :> now; return (float)(SDRAM_ROW_COUNT * ((4*100000000/1024)/1024) * count) / (now-then); } -static float writeWords(chanend server, unsigned count, unsigned page_alignment){ +static float writeWords(chanend c_server, unsigned count, unsigned page_alignment){ unsigned buf[SDRAM_ROW_WORDS]; timer t; unsigned now, then; @@ -30,15 +34,15 @@ static float writeWords(chanend server, unsigned count, unsigned page_alignment) } t :> then; for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_buffer_write(server, 0, row, page_alignment, count, buf); - sdram_wait_until_idle(server, buf); + sdram_buffer_write(c_server, 0, row, page_alignment, count, buf); + sdram_wait_until_idle(c_server, buf); } t :> now; return (float)(SDRAM_ROW_COUNT * ((4*100000000/1024)/1024) * count) / (now-then); } -static float maxWriteWords(chanend server){ +static float maxWriteWords(chanend c_server){ unsigned buf[SDRAM_ROW_WORDS]; timer t; unsigned now, then; @@ -47,30 +51,32 @@ static float maxWriteWords(chanend server){ } t :> then; for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_full_row_write(server,0, row, buf); - sdram_wait_until_idle(server, buf); + sdram_full_row_write(c_server,0, row, buf); + sdram_wait_until_idle(c_server, buf); } t :> now; return (float)(SDRAM_ROW_COUNT * SDRAM_ROW_WORDS * ((4*100000000/1024)/1024)) / (now-then); } -static float maxReadWords(chanend server){ +static float maxReadWords(chanend c_server){ unsigned buf[SDRAM_ROW_WORDS]; timer t; unsigned now, then; t :> then; for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_full_row_read(server, 0, row, buf); - sdram_wait_until_idle(server, buf); + sdram_full_row_read(c_server, 0, row, buf); + sdram_wait_until_idle(c_server, buf); } t :> now; return (float)(SDRAM_ROW_COUNT * SDRAM_ROW_WORDS * ((4*100000000/1024)/1024)) / (now-then); } -void load_thread(chanend in_t, chanend out_t) { + +static void load_thread(chanend in_t, chanend out_t) { set_thread_fast_mode_on(); in_t :> int; out_t <: 1; } -void sanity_check(chanend sdram_c) { + +static void sanity_check(chanend sdram_c) { #define SANITY_TEST_SIZE 8 #define SANITY_TEST_BANK 1 #define SANITY_TEST_ROW 1 @@ -99,26 +105,26 @@ void sanity_check(chanend sdram_c) { if(VERBOSE) printf("\tPassed\n"); } -void speed_regression_single_thread(chanend server, unsigned cores) { - sanity_check(server); +static void speed_regression_single_thread(chanend c_server, unsigned cores) { + sanity_check(c_server); if(VERBOSE){ printf("Words\tWrite\tWrite\tRead\tRead\n"); printf("\tsingle\tmulti\tsingle\tmulti\n"); } for(unsigned word_count = 1; word_count <= SDRAM_ROW_WORDS; word_count++){ - float single_page_write = writeWords(server, word_count, 0); - float multi_page_write = writeWords(server, word_count, SDRAM_ROW_WORDS-1); - float single_page_read = writeWords(server, word_count, 0); - float multi_page_read = writeWords(server, word_count, SDRAM_ROW_WORDS-1); + float single_page_write = writeWords(c_server, word_count, 0); + float multi_page_write = writeWords(c_server, word_count, SDRAM_ROW_WORDS-1); + float single_page_read = writeWords(c_server, word_count, 0); + float multi_page_read = writeWords(c_server, word_count, SDRAM_ROW_WORDS-1); if(VERBOSE) printf("%d\t%.2f\t%.2f\t%.2f\t%.2f\n", word_count, single_page_write, multi_page_write, single_page_read, multi_page_read); } printf("Cores active: %d\n", cores); - printf("Max write: %.2f MB/s\n", maxWriteWords(server)); - printf("Max read : %.2f MB/s\n", maxReadWords(server)); + printf("Max write: %.2f MB/s\n", maxWriteWords(c_server)); + printf("Max read : %.2f MB/s\n", maxReadWords(c_server)); } -{unsigned, unsigned} varWriteWords(chanend server, unsigned count){ +{unsigned, unsigned} varWriteWords(chanend c_server, unsigned count){ unsigned buf[SDRAM_ROW_WORDS]; timer t; unsigned now, then; @@ -130,8 +136,8 @@ void speed_regression_single_thread(chanend server, unsigned cores) { for (unsigned row = 0; row < 10000; row++) { unsigned time; t :> then; - sdram_buffer_write(server, 0, row, 0, count, buf); - sdram_wait_until_idle(server, buf); + sdram_buffer_write(c_server, 0, row, 0, count, buf); + sdram_wait_until_idle(c_server, buf); t :> now; time = now - then; if (time < min) min = time; @@ -141,17 +147,17 @@ void speed_regression_single_thread(chanend server, unsigned cores) { } -void latency_regression_single_thread(chanend server, unsigned cores) { +static void latency_regression_single_thread(chanend c_server, unsigned cores) { unsigned total = 0; unsigned min_results[SDRAM_ROW_WORDS+1]; unsigned max_results[SDRAM_ROW_WORDS+1]; float min_latency=0; float max_latency=0; - sanity_check(server); + sanity_check(c_server); for(unsigned word_count = 1; word_count <= SDRAM_ROW_WORDS; word_count++){ unsigned min, max; - {min, max} = varWriteWords(server, word_count); + {min, max} = varWriteWords(c_server, word_count); total += max; min_results[word_count] = min; max_results[word_count] = max; @@ -167,53 +173,38 @@ void latency_regression_single_thread(chanend server, unsigned cores) { printf("Min Latency: %.2f\nMax Latency: %.2f\n", min_latency, max_latency); } -void regression(chanend server, chanend in_t, chanend out_t, unsigned cores) { - speed_regression_single_thread(server, cores); - latency_regression_single_thread(server, cores); +static void regression(chanend c_server, chanend in_t, chanend out_t, unsigned cores) { + speed_regression_single_thread(c_server, cores); + latency_regression_single_thread(c_server, cores); out_t <: 1; in_t :> int; } -void test_2_threads(chanend server) { - //sdram_server - speed_regression_single_thread(server, 2); - latency_regression_single_thread(server, 2); -} - -void test_3_threads(chanend server) { - chan c[2]; - par { - //sdram_server - regression(server, c[0], c[1], 3); - load_thread(c[1], c[0]); - } -} - -void test_4_threads(chanend server) { +static void test_4_threads(chanend c_server) { chan c[3]; par { - //sdram_server - regression(server, c[0], c[1], 4); + //sdram_c_server + regression(c_server, c[0], c[1], 4); load_thread(c[1], c[2]); load_thread(c[2], c[0]); } } -void test_5_threads(chanend server) { +static void test_5_threads(chanend c_server) { chan c[4]; par { - //sdram_server - regression(server, c[0], c[1], 5); + //sdram_c_server + regression(c_server, c[0], c[1], 5); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[0]); } } -void test_6_threads(chanend server) { +static void test_6_threads(chanend c_server) { chan c[5]; par { - //sdram_server - regression(server, c[0], c[1], 6); + //sdram_c_server + regression(c_server, c[0], c[1], 6); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[4]); @@ -221,11 +212,11 @@ void test_6_threads(chanend server) { } } -void test_7_threads(chanend server) { +static void test_7_threads(chanend c_server) { chan c[6]; par { - //sdram_server - regression(server, c[0], c[1], 7); + //sdram_c_server + regression(c_server, c[0], c[1], 7); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[4]); @@ -234,11 +225,11 @@ void test_7_threads(chanend server) { } } -void test_8_threads(chanend server) { +static void test_8_threads(chanend c_server) { chan c[7]; par { - //sdram_server - regression(server, c[0], c[1], 8); + //sdram_c_server + regression(c_server, c[0], c[1], 8); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[4]); @@ -248,14 +239,12 @@ void test_8_threads(chanend server) { } } -void sdram_client(chanend server) { - test_8_threads(server); - test_7_threads(server); - test_6_threads(server); - test_5_threads(server); - test_4_threads(server); - test_3_threads(server); - test_2_threads(server); +static void sdram_client(chanend c_server) { + test_8_threads(c_server); + test_7_threads(c_server); + test_6_threads(c_server); + test_5_threads(c_server); + test_4_threads(c_server); } int main() { diff --git a/app_sdram_demo/.cproject b/app_sdram_demo/.cproject index 2803108..e9609e5 100644 --- a/app_sdram_demo/.cproject +++ b/app_sdram_demo/.cproject @@ -1,10 +1,10 @@ - + - + @@ -16,7 +16,7 @@ xmake - CONFIG=Debug + all true true @@ -24,7 +24,7 @@ xmake - CONFIG=Debug + clean true true @@ -33,13 +33,13 @@ - + - + - + @@ -153,227 +153,173 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Release - all - true - true - true - - - xmake - CONFIG=Release - clean - true - true - true - - - - - - - - - - - - - - - diff --git a/app_sdram_demo/.project b/app_sdram_demo/.project index b959c2b..27e05c9 100644 --- a/app_sdram_demo/.project +++ b/app_sdram_demo/.project @@ -33,7 +33,7 @@ org.eclipse.cdt.make.core.buildArguments - CONFIG=Debug + org.eclipse.cdt.make.core.buildCommand diff --git a/app_sdram_demo/Makefile b/app_sdram_demo/Makefile index 2f04f71..17cd0b1 100644 --- a/app_sdram_demo/Makefile +++ b/app_sdram_demo/Makefile @@ -1,7 +1,7 @@ # The TARGET variable determines what target system the application is # compiled for. It either refers to an XN file in the source directories # or a valid argument for the --target option when compiling -TARGET = SLICEKIT-L2 +TARGET = SLICEKIT-L16 # The APP_NAME variable determines the name of the final .xe file. It should # not include the .xe postfix. If left blank the name will default to @@ -16,8 +16,7 @@ USED_MODULES = module_sdram module_slicekit_support # XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS # If the variable XCC_MAP_FLAGS is set it overrides the flags passed to # xcc for the final link (mapping) stage. -XCC_FLAGS_Debug = -g -O3 -Wcodes -Xmapper -Wcodes -XCC_FLAGS_Release = -g -O3 -Wcodes -Xmapper -Wcodes +XCC_FLAGS = -g -O3 # The VERBOSE variable, if set to 1, enables verbose output from the make system. VERBOSE = 0 diff --git a/app_sdram_demo/src/app_sdram_demo.xc b/app_sdram_demo/src/app_sdram_demo.xc index 00307d8..8e18822 100644 --- a/app_sdram_demo/src/app_sdram_demo.xc +++ b/app_sdram_demo/src/app_sdram_demo.xc @@ -5,7 +5,12 @@ on tile[0]: sdram_ports ports = { XS1_PORT_16A, XS1_PORT_1B, XS1_PORT_1G, XS1_PORT_1C, XS1_PORT_1F, XS1_CLKBLK_1 }; -void application(chanend server) { +/* + * Plug XA-SK-SDRAM into the STAR slot. + * Ensure `XMOS LINK` is off. Build and run. + */ + +void application(chanend c_server) { #define BUF_WORDS (6) unsigned read_buffer[BUF_WORDS]; unsigned write_buffer[BUF_WORDS]; @@ -17,25 +22,28 @@ void application(chanend server) { } // Write the write_buffer out to SDRAM. - sdram_buffer_write(server, bank, row, col, BUF_WORDS, write_buffer); + sdram_buffer_write(c_server, bank, row, col, BUF_WORDS, write_buffer); //Wait until idle, i.e. the sdram had completed writing. - sdram_wait_until_idle(server, write_buffer); + sdram_wait_until_idle(c_server, write_buffer); // Read the SDRAM into the read_buffer. - sdram_buffer_read(server, bank, row, col, BUF_WORDS, read_buffer); + sdram_buffer_read(c_server, bank, row, col, BUF_WORDS, read_buffer); //Wait until idle, i.e. the sdram had completed reading and hence the data is ready in the buffer. - sdram_wait_until_idle(server, read_buffer); + sdram_wait_until_idle(c_server, read_buffer); for(unsigned i=0;i + - - + + - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + + + xmake + + all + true + true + true + + + xmake + + clean + true + true + true + + - - - - - - + + + + + - + - - @@ -414,38 +434,6 @@ - - - - xmake - CONFIG=Debug - all - true - true - true - - - xmake - CONFIG=Debug - clean - true - true - true - - - - - - - - - - - - - - - @@ -529,347 +517,9 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Debug - all - true - true - true - - - xmake - CONFIG=Debug - clean - true - true - true - - - - + diff --git a/app_sdram_mfg_tests/.project b/app_sdram_mfg_tests/.project index 229b4e7..13a6441 100644 --- a/app_sdram_mfg_tests/.project +++ b/app_sdram_mfg_tests/.project @@ -5,6 +5,16 @@ + + com.xmos.cdt.core.IncludePathBuilder + + + + + com.xmos.cdt.core.ModulePathBuilder + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder clean,full,incremental, @@ -23,7 +33,7 @@ org.eclipse.cdt.make.core.buildArguments - CONFIG=Debug + org.eclipse.cdt.make.core.buildCommand @@ -49,10 +59,6 @@ org.eclipse.cdt.make.core.enableFullBuild true - - org.eclipse.cdt.make.core.environment - XTA_ENABLED=true| - org.eclipse.cdt.make.core.stopOnError true diff --git a/app_sdram_mfg_tests/.xproject b/app_sdram_mfg_tests/.xproject new file mode 100644 index 0000000..1126260 --- /dev/null +++ b/app_sdram_mfg_tests/.xproject @@ -0,0 +1 @@ +sc_sdram_burstXM-001915-SM \ No newline at end of file diff --git a/app_sdram_mfg_tests/Makefile b/app_sdram_mfg_tests/Makefile index 00ca556..c2dfe65 100644 --- a/app_sdram_mfg_tests/Makefile +++ b/app_sdram_mfg_tests/Makefile @@ -1,7 +1,7 @@ # The TARGET variable determines what target system the application is # compiled for. It either refers to an XN file in the source directories # or a valid argument for the --target option when compiling -TARGET = SLICEKIT-L2 +TARGET = SLICEKIT-L16 # The APP_NAME variable determines the name of the final .xe file. It should # not include the .xe postfix. If left blank the name will default to @@ -16,8 +16,7 @@ USED_MODULES = module_sdram module_slicekit_support # XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS # If the variable XCC_MAP_FLAGS is set it overrides the flags passed to # xcc for the final link (mapping) stage. -XCC_FLAGS_Debug = -g -O3 -Wcodes -Xmapper -Wcodes -XCC_FLAGS_Release = -g -O3 -Wcodes -Xmapper -Wcodes +XCC_FLAGS = -g -O3 # The VERBOSE variable, if set to 1, enables verbose output from the make system. VERBOSE = 0 diff --git a/app_sdram_mfg_tests/src/app_sdram_mfg_tests.xc b/app_sdram_mfg_tests/src/app_sdram_mfg_tests.xc index 613aeb8..4c1617b 100644 --- a/app_sdram_mfg_tests/src/app_sdram_mfg_tests.xc +++ b/app_sdram_mfg_tests/src/app_sdram_mfg_tests.xc @@ -5,8 +5,8 @@ /* * This is the SDRAM manafacture test suite. It requires: * WORST_CASE_ACTIVE_CORES - this is the max number of active cores that the sdram - * server must be able to operate during(includes the core - * for the server) + * c_server must be able to operate during(includes the core + * for the c_server) * * Prerequsites * The setup should have been tested with app_sdram_regress and app_sdram_benchmark. @@ -32,19 +32,19 @@ on tile[0]: sdram_ports ports = { * Below here is the test code - there is no need to edit anything below here. */ -static void fillMemory(chanend server, unsigned fill_pattern) { +static void fillMemory(chanend c_server, unsigned fill_pattern) { unsigned buf[SDRAM_ROW_WORDS]; for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) buf[word] = fill_pattern; for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_full_row_write(server, bank, row, buf); - sdram_wait_until_idle(server, buf); + sdram_full_row_write(c_server, bank, row, buf); + sdram_wait_until_idle(c_server, buf); } } } -static void refresh_test(chanend server) { +static void refresh_test(chanend c_server) { unsigned pattern; unsigned wait_multiplier[3] = { 1, 4, 8}; unsigned patterns[3] = { 0, 0x55555555, 0xffffffff }; @@ -54,15 +54,15 @@ static void refresh_test(chanend server) { for (unsigned w = 0; w < 3; w++) { timer t; unsigned time; - fillMemory(server, pattern); + fillMemory(c_server, pattern); for(unsigned tw = 0; tw < wait_multiplier[w]; tw++){ t :> time; t when timerafter(time+100000000):> int; } for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_buffer_read(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - sdram_wait_until_idle(server, buf); + sdram_buffer_read(c_server, bank, row, 0, SDRAM_ROW_WORDS, buf); + sdram_wait_until_idle(c_server, buf); for(unsigned word=0;word>SDRAM_BANK_ADDRESS_BITS) & ((1<>(SDRAM_BANK_ADDRESS_BITS+SDRAM_ROW_ADDRESS_BITS)) - & ((1< max) max = SDRAM_ROW_COUNT; if(SDRAM_COL_COUNT > max) @@ -111,58 +106,22 @@ void address_test(chanend server) { unsigned row = v % SDRAM_ROW_COUNT; unsigned word = v % (SDRAM_ROW_WORDS); - sdram_buffer_read(server, bank, row, word*2, 1, buffer); - sdram_wait_until_idle(server, buffer); + sdram_buffer_read(c_server, bank, row, word*2, 1, buffer); + sdram_wait_until_idle(c_server, buffer); if(makeWord(bank, row, word) != buffer[0]){ - printstrln("Failed address test."); - _Exit(1); + printstrln("Failed address test."); + _Exit(1); } } } -void sanity_check(chanend sdram_c) { -#define SANITY_TEST_SIZE 8 -#define SANITY_TEST_BANK 1 -#define SANITY_TEST_ROW 1 -#define SANITY_TEST_COL 0 - unsigned input_buffer[SANITY_TEST_SIZE]; - unsigned output_buffer[SANITY_TEST_SIZE]; - for (unsigned i = 0; i < SANITY_TEST_SIZE; i++) { - input_buffer[i] = i; - output_buffer[i] = 0xaabbccdd; - } - sdram_buffer_write(sdram_c, SANITY_TEST_BANK, SANITY_TEST_ROW, SANITY_TEST_COL, - SANITY_TEST_SIZE, input_buffer); - sdram_wait_until_idle(sdram_c, input_buffer); - sdram_buffer_read(sdram_c, SANITY_TEST_BANK, SANITY_TEST_ROW, SANITY_TEST_COL, - SANITY_TEST_SIZE, output_buffer); - - sdram_wait_until_idle(sdram_c, output_buffer); - - for (unsigned i = 0; i < SANITY_TEST_SIZE; i++) { - if (i != output_buffer[i]) { - printstrln("Failed sanity check."); - _Exit(1); - } - } -} - -static void wait(){ - timer t; - unsigned w; - t:> w; - t when timerafter (w+1000000) :> w; -} - -void sdram_client(chanend server) { +void sdram_client(chanend c_server) { set_thread_fast_mode_on(); par { { - wait(); - sanity_check(server); - address_test(server); - refresh_test(server); + address_test(c_server); + refresh_test(c_server); printstrln("Success"); _Exit(0); } @@ -176,4 +135,5 @@ int main() { on tile[0]:sdram_server(sdram_c, ports); on tile[0]:sdram_client(sdram_c); } + return 0; } diff --git a/app_sdram_regress/.cproject b/app_sdram_regress/.cproject index 6e1165f..ac91cc7 100644 --- a/app_sdram_regress/.cproject +++ b/app_sdram_regress/.cproject @@ -1,10 +1,10 @@ - + - + @@ -16,7 +16,7 @@ xmake - CONFIG=Debug + all true true @@ -24,7 +24,7 @@ xmake - CONFIG=Debug + clean true true @@ -33,13 +33,13 @@ - + - + - + @@ -153,230 +153,173 @@ - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - xmake - CONFIG=Release - all - true - true - true - - - xmake - CONFIG=Release - clean - true - true - true - - - - - - - - - - - - - - - diff --git a/app_sdram_regress/.project b/app_sdram_regress/.project index 6b792e6..659183e 100644 --- a/app_sdram_regress/.project +++ b/app_sdram_regress/.project @@ -33,7 +33,7 @@ org.eclipse.cdt.make.core.buildArguments - CONFIG=Debug + org.eclipse.cdt.make.core.buildCommand @@ -59,10 +59,6 @@ org.eclipse.cdt.make.core.enableFullBuild true - - org.eclipse.cdt.make.core.environment - XTA_ENABLED=true| - org.eclipse.cdt.make.core.stopOnError true diff --git a/app_sdram_regress/Makefile b/app_sdram_regress/Makefile index f1200f7..c81545e 100644 --- a/app_sdram_regress/Makefile +++ b/app_sdram_regress/Makefile @@ -1,7 +1,7 @@ # The TARGET variable determines what target system the application is # compiled for. It either refers to an XN file in the source directories # or a valid argument for the --target option when compiling -TARGET = SLICEKIT-L2 +TARGET = SLICEKIT-L16 # The APP_NAME variable determines the name of the final .xe file. It should # not include the .xe postfix. If left blank the name will default to @@ -16,8 +16,7 @@ USED_MODULES = module_sdram module_slicekit_support # XCC_XC_FLAGS, XCC_C_FLAGS, XCC_ASM_FLAGS, XCC_CPP_FLAGS # If the variable XCC_MAP_FLAGS is set it overrides the flags passed to # xcc for the final link (mapping) stage. -XCC_FLAGS_Debug = -g -O3 -Wcodes -Xmapper -Wcodes -XCC_FLAGS_Release = -g -O3 -Wcodes -Xmapper -Wcodes +XCC_FLAGS = -g -O3 # The VERBOSE variable, if set to 1, enables verbose output from the make system. VERBOSE = 0 diff --git a/app_sdram_regress/src/app_sdram_regress.xc b/app_sdram_regress/src/app_sdram_regress.xc index 7194ab9..e118235 100644 --- a/app_sdram_regress/src/app_sdram_regress.xc +++ b/app_sdram_regress/src/app_sdram_regress.xc @@ -4,64 +4,67 @@ #include "sdram.h" #define MIN_BLOCK_WIDTH_WORDS 1 + +#define VERBOSE_MSG 1 +#define VERBOSE_ERR 1 + +#if 1 +/* + * Plug XA-SK-SDRAM into the STAR slot. Ensure `XMOS LINK` is off. Build and run. + */ on tile[0]: sdram_ports ports = { - XS1_PORT_16A, XS1_PORT_1B, XS1_PORT_1G, XS1_PORT_1C, XS1_PORT_1F, XS1_CLKBLK_1 }; + XS1_PORT_16A, XS1_PORT_1B, XS1_PORT_1G, XS1_PORT_1C, XS1_PORT_1F, XS1_CLKBLK_1}; +#else +/* + * Plug XA-SK-SDRAM into the TRIANGLE slot. Ensure `XMOS LINK` is off. Build and run. + */ +on tile[0]:sdram_ports ports = { XS1_PORT_16B, XS1_PORT_1J, XS1_PORT_1I, + XS1_PORT_1K, XS1_PORT_1L, XS1_CLKBLK_1 }; +#endif unsigned c = 0xffffffff; -void reset_super_pattern() { +static void reset_super_pattern() { c = 0xffffffff; } -unsigned super_pattern() { +static unsigned super_pattern() { crc32(c, 0xff, 0x82F63B78); return c; } -unsigned pseudo_random_number(unsigned min, unsigned max) { +static unsigned pseudo_random_number(unsigned min, unsigned max) { return super_pattern() % (max + 1 - min) + min; } -static inline void client_write(chanend server, unsigned bank, +static inline void client_write(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned words, unsigned buffer[]) { - sdram_buffer_write(server, bank, start_row, start_col, words, buffer); + sdram_buffer_write(c_server, bank, start_row, start_col, words, buffer); } -static inline void client_read(chanend server, unsigned bank, +static inline void client_read(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned words, unsigned buffer[]) { - sdram_buffer_read(server, bank, start_row, start_col, words, buffer); + sdram_buffer_read(c_server, bank, start_row, start_col, words, buffer); } -static inline void client_wait_until_idle(chanend server, unsigned buffer[]) { - sdram_wait_until_idle(server, buffer); -} - -static void fillMemoryUnique(chanend server) { - unsigned buf[SDRAM_ROW_WORDS]; - for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { - for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) - buf[word] = super_pattern(); - client_write(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - client_wait_until_idle(server, buf); - } - } +static inline void client_wait_until_idle(chanend c_server, unsigned buffer[]) { + sdram_wait_until_idle(c_server, buffer); } -static void fillMemory(chanend server, unsigned fill_pattern) { +static void fillMemory(chanend c_server, unsigned fill_pattern) { unsigned buf[SDRAM_ROW_WORDS]; for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) buf[word] = fill_pattern; for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - sdram_full_row_write(server, bank, row, buf); - sdram_wait_until_idle(server, buf); + sdram_full_row_write(c_server, bank, row, buf); + sdram_wait_until_idle(c_server, buf); } } } -static void fillMemoryExcludingRow(chanend server, unsigned fill_pattern, +static void fillMemoryExcludingRow(chanend c_server, unsigned fill_pattern, unsigned exclusion_bank, unsigned exclusion_row) { unsigned buf[SDRAM_ROW_WORDS]; for (int word = 0; word < SDRAM_ROW_WORDS; word++) @@ -70,45 +73,48 @@ static void fillMemoryExcludingRow(chanend server, unsigned fill_pattern, for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { if (row == exclusion_row && bank == exclusion_bank) continue; - client_write(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - client_wait_until_idle(server, buf); + client_write(c_server, bank, row, 0, SDRAM_ROW_WORDS, buf); + client_wait_until_idle(c_server, buf); } } } -static void single_row_write(chanend server) { +static void single_row_write(chanend c_server) { unsigned buf[SDRAM_ROW_WORDS]; unsigned data = 1; unsigned test_row_count = 8; unsigned test_rows[8] = { 0, 1, 2, 3, SDRAM_ROW_COUNT - 4, SDRAM_ROW_COUNT - 3, SDRAM_ROW_COUNT - 2, SDRAM_ROW_COUNT - 1 }; - printf("Started single_row_write\n"); + if (VERBOSE_MSG) + printf("Started single_row_write\n"); for (int word = 0; word < SDRAM_ROW_WORDS; word++) buf[word] = data; - fillMemory(server, 0xffffffff); + fillMemory(c_server, 0xffffffff); for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned test_row = 0; test_row < test_row_count; test_row++) { unsigned row = test_rows[test_row]; - client_write(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - client_wait_until_idle(server, buf); - fillMemoryExcludingRow(server, 0xffffffff, bank, row); - client_read(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - client_wait_until_idle(server, buf); + client_write(c_server, bank, row, 0, SDRAM_ROW_WORDS, buf); + client_wait_until_idle(c_server, buf); + fillMemoryExcludingRow(c_server, 0xffffffff, bank, row); + client_read(c_server, bank, row, 0, SDRAM_ROW_WORDS, buf); + client_wait_until_idle(c_server, buf); for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) { unsigned b = buf[word]; if (b != data) { - printf("Failed row read on row %d of bank %d: 0x%x != 0\n", row, - bank, b); + if (VERBOSE_ERR) + printf("Failed row read on row %d of bank %d: 0x%x != 0\n", row, + bank, b); _Exit(1); } } } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } -static void partial_row_write_read(chanend server) { +static void partial_row_write_read(chanend c_server) { unsigned reset_buf[SDRAM_ROW_WORDS]; unsigned write_buf[SDRAM_ROW_WORDS]; unsigned read_buf[SDRAM_ROW_WORDS]; @@ -117,34 +123,37 @@ static void partial_row_write_read(chanend server) { unsigned test_rows[8] = { 0, 1, 2, 3, SDRAM_ROW_COUNT - 4, SDRAM_ROW_COUNT - 3, SDRAM_ROW_COUNT - 2, SDRAM_ROW_COUNT - 1 }; - printf("Started partial_row_write_read\n"); + if (VERBOSE_MSG) + printf("Started partial_row_write_read\n"); for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) { reset_buf[word] = 0xffffffff; } - fillMemory(server, 0xffffffff); + fillMemory(c_server, 0xffffffff); for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned r_index = 0; r_index < 8; r_index++) { unsigned row = test_rows[r_index]; for (unsigned start_col = 0; start_col < SDRAM_COL_COUNT; start_col++) { for (unsigned word_count = MIN_BLOCK_WIDTH_WORDS; word_count < (SDRAM_COL_COUNT - start_col) / 2; word_count++) { - client_write(server, bank, row, 0, SDRAM_ROW_WORDS, reset_buf); - client_wait_until_idle(server, reset_buf); + client_write(c_server, bank, row, 0, SDRAM_ROW_WORDS, reset_buf); + client_wait_until_idle(c_server, reset_buf); for (int word = 0; word < word_count; word++) { write_buf[word] = super_pattern(); read_buf[word] = 0xaabbccdd; } - client_write(server, bank, row, start_col, word_count, write_buf); - client_wait_until_idle(server, write_buf); - client_read(server, bank, row, start_col, word_count, read_buf); - client_wait_until_idle(server, read_buf); + client_write(c_server, bank, row, start_col, word_count, write_buf); + client_wait_until_idle(c_server, write_buf); + client_read(c_server, bank, row, start_col, word_count, read_buf); + client_wait_until_idle(c_server, read_buf); for (int word = 0; word < word_count; word++) { unsigned r = read_buf[word]; unsigned w = write_buf[word]; if (r != w) { - printf("Failed row read/write on row %d of bank %d at start_col %d with word_count %d on word %d: read:%08x wrote:%08x\n", - row, bank, start_col, word_count, word, r, w); + if (VERBOSE_ERR) + printf( + "Failed row read/write on row %d of bank %d at start_col %d with word_count %d on word %d: read:%08x wrote:%08x\n", + row, bank, start_col, word_count, word, r, w); _Exit(1); } } @@ -152,11 +161,12 @@ static void partial_row_write_read(chanend server) { } } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } //Check that when we write a section of a row then we are writing to the correct place. -static void partial_row_write_align(chanend server) { +static void partial_row_write_align(chanend c_server) { unsigned reset_buf[SDRAM_ROW_WORDS]; unsigned write_buf[SDRAM_ROW_WORDS]; unsigned read_buf[SDRAM_ROW_WORDS]; @@ -166,13 +176,14 @@ static void partial_row_write_align(chanend server) { unsigned test_rows[8] = { 0, 1, 2, 3, SDRAM_ROW_COUNT - 4, SDRAM_ROW_COUNT - 3, SDRAM_ROW_COUNT - 2, SDRAM_ROW_COUNT - 1 }; - printf("Started partial_row_write_align\n"); + if (VERBOSE_MSG) + printf("Started partial_row_write_align\n"); for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) { reset_buf[word] = 0xffffffff; } - fillMemory(server, 0xffffffff); + fillMemory(c_server, 0xffffffff); for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned r_index = 0; r_index < 8; r_index++) { @@ -191,20 +202,21 @@ static void partial_row_write_align(chanend server) { verify_buf[word + start_col / 2] = sp; } - client_write(server, bank, row, 0, SDRAM_ROW_WORDS, reset_buf); - client_wait_until_idle(server, reset_buf); - client_write(server, bank, row, start_col, word_count, write_buf); - client_wait_until_idle(server, write_buf); - client_read(server, bank, row, 0, SDRAM_ROW_WORDS, read_buf); - client_wait_until_idle(server, read_buf); + client_write(c_server, bank, row, 0, SDRAM_ROW_WORDS, reset_buf); + client_wait_until_idle(c_server, reset_buf); + client_write(c_server, bank, row, start_col, word_count, write_buf); + client_wait_until_idle(c_server, write_buf); + client_read(c_server, bank, row, 0, SDRAM_ROW_WORDS, read_buf); + client_wait_until_idle(c_server, read_buf); for (int word = 0; word < word_count; word++) { unsigned r = read_buf[word]; unsigned v = verify_buf[word]; if (r != v) { - printf( - "Failed row read/write on row %d of bank %d at start_col %d with word_count %d on word %d\n", - row, bank, start_col, word_count, word); + if (VERBOSE_ERR) + printf( + "Failed row read/write on row %d of bank %d at start_col %d with word_count %d on word %d\n", + row, bank, start_col, word_count, word); _Exit(1); } } @@ -212,89 +224,86 @@ static void partial_row_write_align(chanend server) { } } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } -static void whole_mem_write_read(chanend server) { +static void whole_mem_write_read(chanend c_server) { unsigned pattern; unsigned patterns[4] = { 0, 0x55555555, 0xaaaaaaaa, 0xffffffff }; unsigned buf[SDRAM_ROW_WORDS]; - printf("Started whole_mem_write_read\n"); + if (VERBOSE_MSG) + printf("Started whole_mem_write_read\n"); for (unsigned p = 0; p < 4; p++) { pattern = patterns[p]; - fillMemory(server, pattern); + fillMemory(c_server, pattern); for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - client_read(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - client_wait_until_idle(server, buf); + client_read(c_server, bank, row, 0, SDRAM_ROW_WORDS, buf); + client_wait_until_idle(c_server, buf); for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) { unsigned r = buf[word]; if (r != pattern) { - printf("Failed row read/write on row %d of bank %d on word %d\n", - row, bank, word); + if (VERBOSE_ERR) + printf("Failed row read/write on row %d of bank %d on word %d\n", + row, bank, word); } } } } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } -static void refresh_test(chanend server) { +static void refresh_test(chanend c_server) { unsigned pattern; - unsigned wait_multiplier[3] = { 1, 4, 8}; + unsigned wait_multiplier[3] = { 1, 4, 8 }; unsigned patterns[3] = { 0, 0x55555555, 0xffffffff }; unsigned buf[SDRAM_ROW_WORDS]; - printf("Started refresh_test\n"); + if (VERBOSE_MSG) + printf("Started refresh_test\n"); for (unsigned p = 0; p < 3; p++) { pattern = patterns[p]; for (unsigned w = 0; w < 3; w++) { timer t; unsigned time; - fillMemory(server, pattern); - for(unsigned tw = 0; tw < wait_multiplier[w]; tw++){ + fillMemory(c_server, pattern); + for (unsigned tw = 0; tw < wait_multiplier[w]; tw++) { t :> time; t when timerafter(time+100000000):> int; } for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned row = 0; row < SDRAM_ROW_COUNT; row++) { - client_read(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - client_wait_until_idle(server, buf); - for(unsigned word=0;word> 1) & 0xfff, (word >> 13) & 0xff}; -} -*/ -unsigned makeWord(unsigned bank, unsigned row, unsigned word) { - return bank + (row << SDRAM_BANK_ADDRESS_BITS) + (word << (SDRAM_BANK_ADDRESS_BITS+SDRAM_ROW_ADDRESS_BITS)); +static unsigned makeWord(unsigned bank, unsigned row, unsigned word) { + return bank + (row << SDRAM_BANK_ADDRESS_BITS) + (word + << (SDRAM_BANK_ADDRESS_BITS + SDRAM_ROW_ADDRESS_BITS)); } -{unsigned, unsigned, unsigned} unmakeWord(unsigned word) { - return {(word) & ((1<>SDRAM_BANK_ADDRESS_BITS) & ((1<>(SDRAM_BANK_ADDRESS_BITS+SDRAM_ROW_ADDRESS_BITS)) & ((1<> 1) & 0xfff; w = (actual >> 13) & 0xff; - printf("fail pseudo_random_read\n"); + if (VERBOSE_ERR) + printf("fail pseudo_random_read\n"); _Exit(1); } wordsChecked++; } } } - printf("\tCompleted\n"); + if (VERBOSE_MSG) + printf("\tCompleted\n"); } -void ordered_read(chanend server, unsigned test_limit) { - unsigned pass = 0; - printf("Started ordered_read\n"); +static void ordered_read(chanend c_server) { + if (VERBOSE_MSG) + printf("Started ordered_read\n"); { //Init all memory to something unique and predicatable. for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { @@ -358,8 +370,8 @@ void ordered_read(chanend server, unsigned test_limit) { for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) { buffer[word] = makeWord(bank, row, word); } - client_write(server, bank, row, 0, SDRAM_ROW_WORDS, buffer); - client_wait_until_idle(server, buffer); + client_write(c_server, bank, row, 0, SDRAM_ROW_WORDS, buffer); + client_wait_until_idle(c_server, buffer); } } } @@ -371,7 +383,8 @@ void ordered_read(chanend server, unsigned test_limit) { for (unsigned bank = 0; bank < SDRAM_BANK_COUNT - 1; bank++) { for (unsigned width = MIN_BLOCK_WIDTH_WORDS; width < SDRAM_ROW_WORDS - 1; width++) { for (unsigned start_row = 0; start_row < SDRAM_ROW_COUNT - 1; start_row++) { - for (unsigned start_col = 0; start_col < SDRAM_COL_COUNT - 2 * width; start_col += 2) { + for (unsigned start_col = 0; start_col < SDRAM_COL_COUNT - 2 * width; start_col + += 2) { unsigned start_word = start_col / 2; unsigned i = 0; @@ -379,8 +392,8 @@ void ordered_read(chanend server, unsigned test_limit) { for (unsigned x = 0; x < width; x++) buffer[x] = 0; - client_read(server, bank, start_row, start_col, width, buffer); - client_wait_until_idle(server, buffer); + client_read(c_server, bank, start_row, start_col, width, buffer); + client_wait_until_idle(c_server, buffer); for (unsigned word = start_word; word < start_word + width; word++) { unsigned expected = makeWord(bank, start_row, word); @@ -390,7 +403,8 @@ void ordered_read(chanend server, unsigned test_limit) { b = actual & 1; r = (actual >> 1) & 0xfff; w = (actual >> 13) & 0xff; - printf("fail ordered_read %d\n", wordsChecked); + if (VERBOSE_ERR) + printf("fail ordered_read %d\n", wordsChecked); _Exit(1); } wordsChecked++; @@ -400,61 +414,65 @@ void ordered_read(chanend server, unsigned test_limit) { } } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } -void load_thread(chanend in_t, chanend out_t) { +static void load_thread(chanend in_t, chanend out_t) { set_thread_fast_mode_on(); - in_t :> int; + in_t :> int; out_t <: 1; } -static void refresh_test_2(chanend server) { - +static void refresh_test_2(chanend c_server) { unsigned pattern; - unsigned wait_multiplier[3] = { 1, 2, 3}; unsigned patterns[3] = { 0, 0x55555555, 0xffffffff }; - unsigned test_rows[8] = { 0, 1, 2, 3, SDRAM_ROW_COUNT - 4, SDRAM_ROW_COUNT - - 3, SDRAM_ROW_COUNT - 2, SDRAM_ROW_COUNT - 1 }; + unsigned test_rows[8] = { 0, 1, 2, 3, SDRAM_ROW_COUNT - 4, + SDRAM_ROW_COUNT - 3, SDRAM_ROW_COUNT - 2, SDRAM_ROW_COUNT - 1 }; unsigned buf[SDRAM_ROW_WORDS]; - printf("Started refresh_test_2\n"); + if (VERBOSE_MSG) + printf("Started refresh_test_2\n"); for (unsigned p = 0; p < 3; p++) { pattern = patterns[p]; for (unsigned w = 0; w < 3; w++) { - fillMemory(server, pattern); + fillMemory(c_server, pattern); for (unsigned bank = 0; bank < SDRAM_BANK_COUNT; bank++) { for (unsigned t = 0; t < 8; t++) { timer T; unsigned time; unsigned row = test_rows[t]; - client_read(server, bank, row, 0, SDRAM_ROW_WORDS, buf); - T :> time; - T when timerafter(time+100000000):> int; - client_wait_until_idle(server, buf); - for(unsigned word=0;word time; + T when timerafter(time+100000000):> int; + client_wait_until_idle(c_server, buf); + for (unsigned word = 0; word < SDRAM_ROW_WORDS; word++) { unsigned r = buf[word]; - if(r != pattern) { - printf("Failed row read/write on row %d of bank %d on word %d\n", - row, bank, word); + if (r != pattern) { + if (VERBOSE_ERR) + printf( + "Failed row read/write on row %d of bank %d on word %d\n", + row, bank, word); } } } } } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } -void sanity_check(chanend sdram_c) { +static void sanity_check(chanend sdram_c) { #define SANITY_TEST_SIZE 8 #define SANITY_TEST_BANK 1 #define SANITY_TEST_ROW 1 #define SANITY_TEST_COL 0 unsigned input_buffer[SANITY_TEST_SIZE]; unsigned output_buffer[SANITY_TEST_SIZE]; - printf("Begin sanity_check\n"); + if (VERBOSE_MSG) + printf("Begin sanity_check\n"); for (unsigned i = 0; i < SANITY_TEST_SIZE; i++) { input_buffer[i] = i; output_buffer[i] = 0xaabbccdd; @@ -469,66 +487,54 @@ void sanity_check(chanend sdram_c) { for (unsigned i = 0; i < SANITY_TEST_SIZE; i++) { if (i != output_buffer[i]) { - printf("Failed sanity_check on word %d, got word: 0x%08x\n", i, - output_buffer[i]); + if (VERBOSE_ERR) + printf("Failed sanity_check on word %d, got word: 0x%08x\n", i, + output_buffer[i]); _Exit(1); } } - printf("\tPassed\n"); + if (VERBOSE_MSG) + printf("\tPassed\n"); } -void regression_single_thread(chanend server) { +void regression_single_thread(chanend c_server) { reset_super_pattern(); - sanity_check(server); - single_row_write(server); - partial_row_write_read(server); - partial_row_write_align(server); - whole_mem_write_read(server); - refresh_test(server); - refresh_test_2(server); - ordered_read(server, 4096 * 1024); - pseudo_random_read(server, 4096 * 64); -} - -void regression(chanend server, chanend in_t, chanend out_t) { - regression_single_thread(server); + sanity_check(c_server); + single_row_write(c_server); + partial_row_write_read(c_server); + partial_row_write_align(c_server); + whole_mem_write_read(c_server); + refresh_test(c_server); + refresh_test_2(c_server); + ordered_read(c_server); + pseudo_random_read(c_server, 4096 * 16); +} + +void regression(chanend c_server, chanend in_t, chanend out_t) { + regression_single_thread(c_server); out_t <: 1; in_t :> int; } -void test_2_threads(chanend server) { - //sdram_server - printf("2 threaded test suite start\n"); - regression_single_thread(server); - printf("2 threaded test suite completed\n"); -} - -void test_3_threads(chanend server) { - chan c[2]; - printf("3 threaded test suite start\n"); - par { - regression(server, c[0], c[1]); - load_thread(c[1], c[0]); - } - printf("3 threaded test suite completed\n"); -} - -void test_4_threads(chanend server) { +void test_4_threads(chanend c_server) { chan c[3]; - printf("4 threaded test suite start\n"); + if (VERBOSE_MSG) + printf("4 threaded test suite start\n"); par { - regression(server, c[0], c[1]); + regression(c_server, c[0], c[1]); load_thread(c[1], c[2]); load_thread(c[2], c[0]); } - printf("4 threaded test suite completed\n"); + if (VERBOSE_MSG) + printf("4 threaded test suite completed\n"); } -void test_8_threads(chanend server) { +void test_8_threads(chanend c_server) { chan c[7]; - printf("8 threaded test suite start\n"); + if (VERBOSE_MSG) + printf("8 threaded test suite start\n"); par { - regression(server, c[0], c[1]); + regression(c_server, c[0], c[1]); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[4]); @@ -536,65 +542,71 @@ void test_8_threads(chanend server) { load_thread(c[5], c[6]); load_thread(c[6], c[0]); } - printf("8 threaded test suite completed\n"); + if (VERBOSE_MSG) + printf("8 threaded test suite completed\n"); } -void test_7_threads(chanend server) { +void test_7_threads(chanend c_server) { chan c[6]; - printf("7 threaded test suite start\n"); + if (VERBOSE_MSG) + printf("7 threaded test suite start\n"); par { - regression(server, c[0], c[1]); + regression(c_server, c[0], c[1]); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[4]); load_thread(c[4], c[5]); load_thread(c[5], c[0]); } - printf("7 threaded test suite completed\n"); + if (VERBOSE_MSG) + printf("7 threaded test suite completed\n"); } -void test_6_threads(chanend server) { +void test_6_threads(chanend c_server) { chan c[5]; - printf("6 threaded test suite start\n"); + if (VERBOSE_MSG) + printf("6 threaded test suite start\n"); par { - regression(server, c[0], c[1]); + regression(c_server, c[0], c[1]); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[4]); load_thread(c[4], c[0]); } - printf("6 threaded test suite completed\n"); + if (VERBOSE_MSG) + printf("6 threaded test suite completed\n"); } -void test_5_threads(chanend server) { +void test_5_threads(chanend c_server) { chan c[4]; - printf("5 threaded test suite start\n"); + if (VERBOSE_MSG) + printf("5 threaded test suite start\n"); par { - regression(server, c[0], c[1]); + regression(c_server, c[0], c[1]); load_thread(c[1], c[2]); load_thread(c[2], c[3]); load_thread(c[3], c[0]); } - printf("5 threaded test suite completed\n"); + if (VERBOSE_MSG) + printf("5 threaded test suite completed\n"); } -void sdram_client(chanend server) { +void sdram_client(chanend c_server) { set_thread_fast_mode_on(); - while(1){ + if (VERBOSE_MSG) printf("Test suite begin\n"); - test_8_threads(server); - test_7_threads(server); - test_6_threads(server); - test_5_threads(server); - test_4_threads(server); - test_3_threads(server); - test_2_threads(server); + test_8_threads(c_server); + test_7_threads(c_server); + test_6_threads(c_server); + test_5_threads(c_server); + test_4_threads(c_server); + if (VERBOSE_MSG) printf("Test suite completed\n"); - } + sdram_shutdown(c_server); } int main() { chan sdram_c; par { + on tile[0]:sdram_client(sdram_c); on tile[0]:sdram_server(sdram_c, ports); - on tile[0]: sdram_client(sdram_c); } return 0; } diff --git a/doc/api.rst b/doc/api.rst index dc75b47..99776ef 100644 --- a/doc/api.rst +++ b/doc/api.rst @@ -125,6 +125,7 @@ C Interface C and XC Interface ------------------ .. doxygenfunction:: sdram_col_write +.. doxygenfunction:: sdram_shutdown SDRAM Memory Mapper API ----------------------- diff --git a/doc/examples.rst b/doc/examples.rst index 11791b9..cb92b06 100644 --- a/doc/examples.rst +++ b/doc/examples.rst @@ -20,12 +20,12 @@ Getting Started The output produced should look like:: - 0 0 - 1 1 - 2 2 - 3 3 - 4 4 - 5 5 + 00000000 00000000 + 00000001 00000001 + 00000002 00000002 + 00000003 00000003 + 00000004 00000004 + 00000005 00000005 SDRAM demo complete. Notes @@ -47,7 +47,7 @@ Getting Started #. Open ``app_sdram_regress.xc`` and build it. #. run the program on the hardware. -The output produced should look like:: +With verbose output turned on (controlled by VERBOSE_MSG and VERBOSE_ERR), the output produced should look like:: Test suite begin 8 threaded test suite start diff --git a/module_sdram/.cproject b/module_sdram/.cproject index 3cedc18..9983662 100644 --- a/module_sdram/.cproject +++ b/module_sdram/.cproject @@ -1,4 +1,4 @@ - + @@ -153,27 +153,258 @@ - - + diff --git a/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.h b/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.h index fd70ad3..55f9ab0 100644 --- a/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.h +++ b/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.h @@ -3,6 +3,6 @@ #include "sdram_ports_PINOUT_V0.h" -void sdram_server_PINOUT_V0(chanend client, struct sdram_ports_PINOUT_V0 &ports); +void sdram_server_PINOUT_V0(chanend c_client, struct sdram_ports_PINOUT_V0 &ports); #endif diff --git a/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.xc b/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.xc index 8dd1da0..93455b0 100644 --- a/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.xc +++ b/module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.xc @@ -13,18 +13,16 @@ void sdram_init_PINOUT_V0(struct sdram_ports_PINOUT_V0 &p) { timer T; int t, time; - asm("setc res[%0], 0x200F" :: "r"(p.dq_ah)); - asm("settw res[%0], %1" :: "r"(p.dq_ah), "r"(32)); + p.cas <: 0; + p.ras <: 0; + p.we <: 0; + p.dq_ah <: 0; - p.cke <: 0 @ t; - - partout_timed(p.cas, 1, CTRL_CAS_NOP, t+32); - partout_timed(p.ras, 1, CTRL_RAS_NOP, t+32); - partout_timed(p.we, 1, CTRL_WE_NOP, t+32); + sync(p.dq_ah); stop_clock(p.cb); T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; set_clock_div(p.cb, 1); set_port_clock(p.clk, p.cb); @@ -40,44 +38,32 @@ void sdram_init_PINOUT_V0(struct sdram_ports_PINOUT_V0 &p) { p.dqm <: 0; - T :> t; - - T when timerafter(t + 50 * TIMER_TICKS_PER_US) :> t; + T :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; p.cke <: 1; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> t; + T :> time; + T when timerafter(time + 50 * TIMER_TICKS_PER_US) :> time; - p.dq_ah <: 0x04000400 @ t; + p.dq_ah @ t <: 0x04000400; - t+=60; + t += 60; partout_timed(p.ras, 2, CTRL_RAS_PRECHARGE | (CTRL_RAS_NOP<<1), t); partout_timed(p.we, 2, CTRL_WE_PRECHARGE | (CTRL_WE_NOP<<1), t); - t+=8; - - partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); - partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); - t+=8; + t += 8; - partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); - partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); - t+=8; - - partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); - partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); - t+=8; - - partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); - partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); - t+=8; + for(unsigned i=0;i<128;i++){ + partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); + partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); + t += 8; + } // set mode register p.dq_ah @ t<: (SDRAM_MODE_REGISTER << 16)|SDRAM_MODE_REGISTER; - t+=32; - - //do 16 nops - t+=16; + sync(p.dq_ah); + t += 48; partout_timed(p.cas, 2, CTRL_CAS_LOAD_MODEREG | (CTRL_CAS_NOP<<1), t); partout_timed(p.ras, 2, CTRL_RAS_LOAD_MODEREG | (CTRL_RAS_NOP<<1), t); @@ -94,23 +80,27 @@ void sdram_init_PINOUT_V0(struct sdram_ports_PINOUT_V0 &p) { #define RAS_QUAD_REFRESH (RAS_DOUBLE_REFRESH | (RAS_DOUBLE_REFRESH<<8)) #define RAS_OCTUPLE_REFRESH (RAS_QUAD_REFRESH | (RAS_QUAD_REFRESH<<16)) -static inline void sdram_refresh_PINOUT_V0(unsigned ncycles, struct sdram_ports_PINOUT_V0 &p) { +static inline void sdram_refresh_PINOUT_V0(unsigned ncycles, + struct sdram_ports_PINOUT_V0 &p) { unsigned t; t = partout_timestamped(p.cas, 1, CTRL_CAS_NOP); - t+=20; - for (unsigned i = 0; i < ncycles; i+=8){ - t+=32; - partout_timed(p.cas, 32, CAS_OCTUPLE_REFRESH, t); - partout_timed(p.ras, 32, RAS_OCTUPLE_REFRESH, t); + t += 20; + for (unsigned i = 0; i < ncycles; i += 8) { + t += 32; + partout_timed(p.cas, 32, CAS_OCTUPLE_REFRESH, t); + partout_timed(p.ras, 32, RAS_OCTUPLE_REFRESH, t); } } -void sdram_block_write_PINOUT_V0(unsigned buffer, unsigned word_count, out port dq, - out buffered port:8 we, out buffered port:32 ras, unsigned term_time); -void sdram_block_read_PINOUT_V0(unsigned buffer, unsigned word_count, out port dq, - out buffered port:8 ctrl, unsigned term_time, unsigned st, out buffered port:32 ras); -void sdram_short_block_read_PINOUT_V0(unsigned buffer, unsigned word_count, out port dq, - out buffered port:8 ctrl, unsigned term_time, unsigned st, out buffered port:32 ras); +void sdram_block_write_PINOUT_V0(unsigned buffer, unsigned word_count, + out port dq, out buffered port:8 we, out buffered port:32 ras, + unsigned term_time); +void sdram_block_read_PINOUT_V0(unsigned buffer, unsigned word_count, + out port dq, out buffered port:8 ctrl, unsigned term_time, unsigned st, + out buffered port:32 ras); +void sdram_short_block_read_PINOUT_V0(unsigned buffer, unsigned word_count, + out port dq, out buffered port:8 ctrl, unsigned term_time, unsigned st, + out buffered port:32 ras); /* * These numbers are tuned for 50MIPS. @@ -119,63 +109,64 @@ void sdram_short_block_read_PINOUT_V0(unsigned buffer, unsigned word_count, out #define WRITE_COL_SETUP_LATENCY (50) #define READ_SETUP_LATENCY (50) -static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V0] = - {(0<<13) | (0<<(13+16) | 1<<(10+16)), - (1<<13) | (1<<(13+16) | 1<<(10+16)), - (2<<13) | (2<<(13+16) | 1<<(10+16)), - (3<<13) | (3<<(13+16) | 1<<(10+16))}; +static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V0] = { (0 << 13) | (0 + << (13 + 16) | 1 << (10 + 16)), (1 << 13) | (1 << (13 + 16) | 1 + << (10 + 16)), (2 << 13) | (2 << (13 + 16) | 1 << (10 + 16)), (3 << 13) + | (3 << (13 + 16) | 1 << (10 + 16)) }; #pragma unsafe arrays -static inline void sdram_write_PINOUT_V0(unsigned row, unsigned col, unsigned bank, - unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V0 &ports) { - - unsigned t; - unsigned stop_time; - unsigned jump; - unsigned rowcol; +static inline void sdram_write_PINOUT_V0(unsigned row, unsigned col, + unsigned bank, unsigned buffer, unsigned word_count, + struct sdram_ports_PINOUT_V0 &ports) { - #ifdef EXTERNAL_MEMORY_ACCESSOR - if (col) { - col = col - 1; - } else { - col = (SDRAM_COL_COUNT - 1); - } - #endif + unsigned t; + unsigned stop_time; + unsigned jump; + unsigned rowcol; - rowcol = (col << 16) | row | bank_table[bank]; + if (SDRAM_EXTERNAL_MEMORY_ACCESSOR) { + if (col) { + col = col - 1; + } else { + col = (SDRAM_COL_COUNT_PINOUT_V0 - 1); + } + } - //adjust the buffer - buffer -= 4 * (SDRAM_ROW_WORDS_PINOUT_V0 - word_count); - jump = 2 * (SDRAM_ROW_WORDS_PINOUT_V0 - word_count); + rowcol = (col << 16) | row | bank_table[bank]; - t = partout_timestamped(ports.dqm, 1, 0); + //adjust the buffer + buffer -= 4 * (SDRAM_ROW_WORDS_PINOUT_V0 - word_count); + jump = 2 * (SDRAM_ROW_WORDS_PINOUT_V0 - word_count); - t += WRITE_SETUP_LATENCY; - stop_time = t + (word_count << 1) + 2; + t = partout_timestamped(ports.dqm, 1, 0); - ports.dq_ah @ t<: rowcol; + t += WRITE_SETUP_LATENCY; + stop_time = t + (word_count << 1) + 2; - partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_WRITE<<1) | (CTRL_CAS_NOP<<2), t); - partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2), t); - partout_timed(ports.we , 3, CTRL_WE_ACTIVE | (CTRL_WE_WRITE<<1) | (CTRL_WE_NOP<<2), t); + ports.dq_ah @ t<: rowcol; - ports.dqm @ t <: 0x2; + partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_WRITE<<1) | (CTRL_CAS_NOP<<2), t); + partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2), t); + partout_timed(ports.we , 3, CTRL_WE_ACTIVE | (CTRL_WE_WRITE<<1) | (CTRL_WE_NOP<<2), t); + ports.dqm @ t <: 0x2; - sdram_block_write_PINOUT_V0(buffer, jump, ports.dq_ah, ports.we, ports.ras, stop_time); + sdram_block_write_PINOUT_V0(buffer, jump, ports.dq_ah, ports.we, ports.ras, + stop_time); } #pragma unsafe arrays -static inline void sdram_col_write_PINOUT_V0(unsigned bank, unsigned row, unsigned col, - short data, struct sdram_ports_PINOUT_V0 &ports) { +static inline void sdram_col_write_PINOUT_V0(unsigned bank, unsigned row, + unsigned col, short data, struct sdram_ports_PINOUT_V0 &ports) { unsigned t; unsigned data_stop; unsigned rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) - if (col) - col = col - 1; - else - col = (SDRAM_COL_COUNT_PINOUT_V0 - 1); + if (SDRAM_EXTERNAL_MEMORY_ACCESSOR) { + if (col) + col = col - 1; + else + col = (SDRAM_COL_COUNT_PINOUT_V0 - 1); + } rowcol = (col << 16) | row | bank_table[bank]; data_stop = (data << 16) | 0xffff; @@ -192,52 +183,55 @@ static inline void sdram_col_write_PINOUT_V0(unsigned bank, unsigned row, unsign } #pragma unsafe arrays -static inline void sdram_read_PINOUT_V0(unsigned row, unsigned col, unsigned bank, - unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V0 &ports) { +static inline void sdram_read_PINOUT_V0(unsigned row, unsigned col, + unsigned bank, unsigned buffer, unsigned word_count, + struct sdram_ports_PINOUT_V0 &ports) { unsigned t; unsigned stop_time; unsigned jump; unsigned rowcol; -#ifdef EXTERNAL_MEMORY_ACCESSOR - if (col) { - col = col - 1; - } else { - col = (SDRAM_COL_COUNT - 1); + if (SDRAM_EXTERNAL_MEMORY_ACCESSOR) { + if (col) { + col = col - 1; + } else { + col = (SDRAM_COL_COUNT_PINOUT_V0 - 1); + } } -#endif rowcol = bank_table[bank] | (col << 16) | row; if (word_count < 4) { - t = partout_timestamped(ports.dqm, 1, 0); - t += READ_SETUP_LATENCY; - stop_time = t + (4 << 1) + 4; + t = partout_timestamped(ports.dqm, 1, 0); + t += READ_SETUP_LATENCY; + stop_time = t + (4 << 1) + 4; - ports.dq_ah @ t <: rowcol; + ports.dq_ah @ t <: rowcol; - partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_READ<<1) | (CTRL_CAS_NOP<<2), t); - partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_READ<<1) | (CTRL_RAS_NOP<<2), t); + partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_READ<<1) | (CTRL_CAS_NOP<<2), t); + partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_READ<<1) | (CTRL_RAS_NOP<<2), t); - sdram_short_block_read_PINOUT_V0(buffer, word_count, ports.dq_ah, ports.we, stop_time, t+3, ports.ras); + sdram_short_block_read_PINOUT_V0(buffer, word_count, ports.dq_ah, ports.we, + stop_time, t + 3, ports.ras); } else { - //adjust the buffer - buffer -= 4 * (0x3f&(SDRAM_ROW_WORDS_PINOUT_V0 - word_count)); - jump = 2 * (SDRAM_ROW_WORDS_PINOUT_V0 - word_count); + //adjust the buffer + buffer -= 4 * (0x3f & (SDRAM_ROW_WORDS_PINOUT_V0 - word_count)); + jump = 2 * (SDRAM_ROW_WORDS_PINOUT_V0 - word_count); - t = partout_timestamped(ports.dqm, 1, 0); - t+= READ_SETUP_LATENCY; - stop_time = t + (word_count<<1)+4; + t = partout_timestamped(ports.dqm, 1, 0); + t += READ_SETUP_LATENCY; + stop_time = t + (word_count << 1) + 4; - ports.dq_ah @ t <: rowcol; - partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_READ<<1) | (CTRL_CAS_NOP<<2), t); - partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_READ<<1) | (CTRL_RAS_NOP<<2), t); + ports.dq_ah @ t <: rowcol; + partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_READ<<1) | (CTRL_CAS_NOP<<2), t); + partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_READ<<1) | (CTRL_RAS_NOP<<2), t); - sdram_block_read_PINOUT_V0(buffer, jump, ports.dq_ah, ports.we, stop_time, t+3, ports.ras); + sdram_block_read_PINOUT_V0(buffer, jump, ports.dq_ah, ports.we, stop_time, + t + 3, ports.ras); } } diff --git a/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.h b/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.h index 586c955..72675e4 100644 --- a/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.h +++ b/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.h @@ -3,6 +3,6 @@ #include "sdram_ports_PINOUT_V1_IS42S16160D.h" -void sdram_server_PINOUT_V1_IS42S16160D(chanend client, struct sdram_ports_PINOUT_V1_IS42S16160D &ports); +void sdram_server_PINOUT_V1_IS42S16160D(chanend c_client, struct sdram_ports_PINOUT_V1_IS42S16160D &ports); #endif diff --git a/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.xc b/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.xc index c9f8468..06d6bea 100644 --- a/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.xc +++ b/module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.xc @@ -9,74 +9,73 @@ #define TIMER_TICKS_PER_US PLATFORM_REFERENCE_MHZ -void sdram_init_PINOUT_V1_IS42S16160D(struct sdram_ports_PINOUT_V1_IS42S16160D &p) { - timer T; - int time, t; +void sdram_init_PINOUT_V1_IS42S16160D( + struct sdram_ports_PINOUT_V1_IS42S16160D &p) { + timer T; + int time, t; - p.cas <: 0; - p.ras <: 0; - p.we <: 0; - p.dq_ah <: 0; + p.cas <: 0; + p.ras <: 0; + p.we <: 0; + p.dq_ah <: 0; - stop_clock(p.cb); + sync(p.dq_ah); + stop_clock(p.cb); - T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; - set_clock_div(p.cb, SDRAM_CLOCK_DIVIDER); - set_port_clock(p.clk, p.cb); - set_port_mode_clock(p.clk); + set_clock_div(p.cb, SDRAM_CLOCK_DIVIDER); + set_port_clock(p.clk, p.cb); + set_port_mode_clock(p.clk); - set_port_clock(p.dq_ah, p.cb); - set_port_clock(p.cas, p.cb); - set_port_clock(p.ras, p.cb); - set_port_clock(p.we, p.cb); - set_port_sample_delay(p.dq_ah); - start_clock(p.cb); + set_port_clock(p.dq_ah, p.cb); + set_port_clock(p.cas, p.cb); + set_port_clock(p.ras, p.cb); + set_port_clock(p.we, p.cb); + set_port_sample_delay(p.dq_ah); + start_clock(p.cb); - p.dq_ah <: 0 @ t; - t+=20; + p.dq_ah <: 0 @ t; + t += 20; - partout(p.cas,1, 0); - partout(p.we, 1, 0); + partout(p.cas,1, 0); + partout(p.we, 1, 0); - T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; - p.dq_ah <: 0 @ t; - t+=20; - partout_timed(p.ras,1, CTRL_RAS_NOP, t); - partout_timed(p.cas,1, CTRL_CAS_NOP, t); - partout_timed(p.we, 1, CTRL_WE_NOP, t); + p.dq_ah <: 0 @ t; + t += 20; + partout_timed(p.ras,1, CTRL_RAS_NOP, t); + partout_timed(p.cas,1, CTRL_CAS_NOP, t); + partout_timed(p.we, 1, CTRL_WE_NOP, t); - T :> time; - T when timerafter(t + 50 * TIMER_TICKS_PER_US) :> time; + T :> time; + T when timerafter(time + 50 * TIMER_TICKS_PER_US) :> time; - p.dq_ah <: 0x04000400 @ t; + p.dq_ah <: 0x04000400 @ t; - t+=60; + t += 60; - partout_timed(p.ras, 2, CTRL_RAS_PRECHARGE | (CTRL_RAS_NOP<<1), t); - partout_timed(p.we, 2, CTRL_WE_PRECHARGE | (CTRL_WE_NOP<<1), t); - t+=8; + partout_timed(p.ras, 2, CTRL_RAS_PRECHARGE | (CTRL_RAS_NOP<<1), t); + partout_timed(p.we, 2, CTRL_WE_PRECHARGE | (CTRL_WE_NOP<<1), t); + t += 8; - for(unsigned i=0;i<128;i++){ - partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); - partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); - t+=8; - } - - // set mode register - p.dq_ah @ t<: (SDRAM_MODE_REGISTER << 16)|SDRAM_MODE_REGISTER; - t+=32; - - //do 16 nops - t+=16; + for (unsigned i = 0; i < 128; i++) { + partout_timed(p.cas, 2, CTRL_CAS_REFRESH | (CTRL_CAS_NOP<<1), t); + partout_timed(p.ras, 2, CTRL_RAS_REFRESH | (CTRL_RAS_NOP<<1), t); + t += 8; + } - partout_timed(p.cas, 2, CTRL_CAS_LOAD_MODEREG | (CTRL_CAS_NOP<<1), t); - partout_timed(p.ras, 2, CTRL_RAS_LOAD_MODEREG | (CTRL_RAS_NOP<<1), t); - partout_timed(p.we, 2, CTRL_WE_LOAD_MODEREG | (CTRL_WE_NOP<<1), t); + // set mode register + p.dq_ah @ t<: (SDRAM_MODE_REGISTER << 16)|SDRAM_MODE_REGISTER; + sync(p.dq_ah); + t += 48; + partout_timed(p.cas, 2, CTRL_CAS_LOAD_MODEREG | (CTRL_CAS_NOP<<1), t); + partout_timed(p.ras, 2, CTRL_RAS_LOAD_MODEREG | (CTRL_RAS_NOP<<1), t); + partout_timed(p.we, 2, CTRL_WE_LOAD_MODEREG | (CTRL_WE_NOP<<1), t); } #if (SDRAM_CMDS_PER_REFRESH==2) @@ -100,23 +99,27 @@ void sdram_init_PINOUT_V1_IS42S16160D(struct sdram_ports_PINOUT_V1_IS42S16160D & #define RAS_QUAD_REFRESH (RAS_DOUBLE_REFRESH | (RAS_DOUBLE_REFRESH<<(SDRAM_CMDS_PER_REFRESH*2))) #define RAS_OCTUPLE_REFRESH (RAS_QUAD_REFRESH | (RAS_QUAD_REFRESH<<(SDRAM_CMDS_PER_REFRESH*4))) -static inline void sdram_refresh_PINOUT_V1_IS42S16160D(unsigned ncycles, struct sdram_ports_PINOUT_V1_IS42S16160D &p) { +static inline void sdram_refresh_PINOUT_V1_IS42S16160D(unsigned ncycles, + struct sdram_ports_PINOUT_V1_IS42S16160D &p) { unsigned t; t = partout_timestamped(p.cas, 1, CTRL_CAS_NOP); - t+=20; - for (unsigned i = 0; i < ncycles; i+=8){ - t+=(8*SDRAM_CMDS_PER_REFRESH); - partout_timed(p.cas, 8*SDRAM_CMDS_PER_REFRESH, CAS_OCTUPLE_REFRESH, t); - partout_timed(p.ras, 8*SDRAM_CMDS_PER_REFRESH, RAS_OCTUPLE_REFRESH, t); + t += 20; + for (unsigned i = 0; i < ncycles; i += 8) { + t += (8 * SDRAM_CMDS_PER_REFRESH); + partout_timed(p.cas, 8*SDRAM_CMDS_PER_REFRESH, CAS_OCTUPLE_REFRESH, t); + partout_timed(p.ras, 8*SDRAM_CMDS_PER_REFRESH, RAS_OCTUPLE_REFRESH, t); } } -void sdram_block_write_PINOUT_V1_IS42S16160D(unsigned buffer, unsigned word_count, buffered port:32 dq, - out buffered port:8 we, out buffered port:32 ras, unsigned term_time); -void sdram_block_read_PINOUT_V1_IS42S16160D(unsigned buffer, unsigned word_count, buffered port:32 dq, - out buffered port:8 ctrl, unsigned term_time, unsigned st, out buffered port:32 ras); -void sdram_short_block_read_PINOUT_V1_IS42S16160D(unsigned buffer, unsigned word_count, buffered port:32 dq, - out buffered port:8 ctrl, unsigned term_time, unsigned st, out buffered port:32 ras); +void sdram_block_write_PINOUT_V1_IS42S16160D(unsigned buffer, + unsigned word_count, buffered port:32 dq, out buffered port:8 we, + out buffered port:32 ras, unsigned term_time); +void sdram_block_read_PINOUT_V1_IS42S16160D(unsigned buffer, + unsigned word_count, buffered port:32 dq, out buffered port:8 ctrl, + unsigned term_time, unsigned st, out buffered port:32 ras); +void sdram_short_block_read_PINOUT_V1_IS42S16160D(unsigned buffer, + unsigned word_count, buffered port:32 dq, out buffered port:8 ctrl, + unsigned term_time, unsigned st, out buffered port:32 ras); /* * These numbers are tuned for 50MIPS. @@ -125,19 +128,18 @@ void sdram_short_block_read_PINOUT_V1_IS42S16160D(unsigned buffer, unsigned word #define WRITE_COL_SETUP_LATENCY (80) #define READ_SETUP_LATENCY (80) -static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V1_IS42S16160D] = - {(0<<13) | (0<<(13+16) | 1<<(10+16)), - (1<<13) | (1<<(13+16) | 1<<(10+16)), - (2<<13) | (2<<(13+16) | 1<<(10+16)), - (3<<13) | (3<<(13+16) | 1<<(10+16))}; +static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V1_IS42S16160D] = { + (0 << 13) | (0 << (13 + 16) | 1 << (10 + 16)), (1 << 13) | (1 << (13 + 16) + | 1 << (10 + 16)), (2 << 13) | (2 << (13 + 16) | 1 << (10 + 16)), (3 + << 13) | (3 << (13 + 16) | 1 << (10 + 16)) }; #define MIN(a,b) (((a)<(b))?(a):(b)) #define MAX_WORDS_PER_WRITE 128 - #pragma unsafe arrays -static inline void sdram_write_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, unsigned bank, - unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V1_IS42S16160D &ports) { +static inline void sdram_write_PINOUT_V1_IS42S16160D(unsigned row, + unsigned col, unsigned bank, unsigned buffer, unsigned word_count, + struct sdram_ports_PINOUT_V1_IS42S16160D &ports) { unsigned t; unsigned stop_time; unsigned jump; @@ -145,13 +147,14 @@ static inline void sdram_write_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, unsigned rem_words = word_count; - while(rem_words){ + while (rem_words) { unsigned words = MIN(rem_words, MAX_WORDS_PER_WRITE); - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) + if (SDRAM_EXTERNAL_MEMORY_ACCESSOR) { if (col) col = col - 1; else col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16160D - 1); + } rowcol = (col << 16) | row | bank_table[bank]; //adjust the buffer @@ -169,26 +172,28 @@ static inline void sdram_write_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2), t); partout_timed(ports.we , 3, CTRL_WE_ACTIVE | (CTRL_WE_WRITE<<1) | (CTRL_WE_NOP<<2), t); - sdram_block_write_PINOUT_V1_IS42S16160D(buffer, jump, ports.dq_ah, ports.we, ports.ras, stop_time); + sdram_block_write_PINOUT_V1_IS42S16160D(buffer, jump, ports.dq_ah, + ports.we, ports.ras, stop_time); rem_words -= words; - col += 2*words; + col += 2 * words; buffer += 4 * words; } } #pragma unsafe arrays -static inline void sdram_col_write_PINOUT_V1_IS42S16160D(unsigned bank, unsigned row, unsigned col, - short data, struct sdram_ports_PINOUT_V1_IS42S16160D &ports) { +static inline void sdram_col_write_PINOUT_V1_IS42S16160D(unsigned bank, + unsigned row, unsigned col, short data, + struct sdram_ports_PINOUT_V1_IS42S16160D &ports) { unsigned t; unsigned data_stop; unsigned rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) - if (col) - col = col - 1; - else - col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16160D - 1); - + if (SDRAM_EXTERNAL_MEMORY_ACCESSOR) { + if (col) + col = col - 1; + else + col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16160D - 1); + } rowcol = (col << 16) | row | bank_table[bank]; data_stop = (data << 16) | 0xffff; t = partout_timestamped(ports.cas, 1, CTRL_WE_NOP); @@ -203,19 +208,20 @@ static inline void sdram_col_write_PINOUT_V1_IS42S16160D(unsigned bank, unsigned } #pragma unsafe arrays -static inline void sdram_read_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, unsigned bank, - unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V1_IS42S16160D &ports) { +static inline void sdram_read_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, + unsigned bank, unsigned buffer, unsigned word_count, + struct sdram_ports_PINOUT_V1_IS42S16160D &ports) { unsigned t, stop_time, jump, rowcol; unsigned rem_words = word_count; - while(rem_words){ - unsigned words = MIN(rem_words, MAX_WORDS_PER_WRITE); - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) + while (rem_words) { + unsigned words = MIN(rem_words, MAX_WORDS_PER_WRITE); + if (SDRAM_EXTERNAL_MEMORY_ACCESSOR){ if (col) col = col - 1; else col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16160D - 1); - + } rowcol = bank_table[bank] | (col << 16) | row; if (words < 4) { @@ -227,23 +233,25 @@ static inline void sdram_read_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_READ<<1) | (CTRL_CAS_NOP<<2), t); partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_READ<<1) | (CTRL_RAS_NOP<<2), t); - sdram_short_block_read_PINOUT_V1_IS42S16160D(buffer, words, ports.dq_ah, ports.we, stop_time, t+3, ports.ras); + sdram_short_block_read_PINOUT_V1_IS42S16160D(buffer, words, ports.dq_ah, + ports.we, stop_time, t + 3, ports.ras); } else { - buffer -= 4 * (0x3f&(MAX_WORDS_PER_WRITE - words)); + buffer -= 4 * (0x3f & (MAX_WORDS_PER_WRITE - words)); jump = 2 * (MAX_WORDS_PER_WRITE - words); t = partout_timestamped(ports.ras, 1, CTRL_WE_NOP); - t+= READ_SETUP_LATENCY; - stop_time = t + (words<<1)+4; + t += READ_SETUP_LATENCY; + stop_time = t + (words << 1) + 4; ports.dq_ah @ t <: rowcol; partout_timed(ports.cas, 3, CTRL_CAS_ACTIVE | (CTRL_CAS_READ<<1) | (CTRL_CAS_NOP<<2), t); partout_timed(ports.ras, 3, CTRL_RAS_ACTIVE | (CTRL_RAS_READ<<1) | (CTRL_RAS_NOP<<2), t); - sdram_block_read_PINOUT_V1_IS42S16160D(buffer, jump, ports.dq_ah, ports.we, stop_time, t+3, ports.ras); + sdram_block_read_PINOUT_V1_IS42S16160D(buffer, jump, ports.dq_ah, + ports.we, stop_time, t + 3, ports.ras); } rem_words -= words; - col += 2*words; + col += 2 * words; buffer += 4 * words; } diff --git a/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.h b/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.h index 1f8f747..6fed69b 100644 --- a/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.h +++ b/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.h @@ -3,6 +3,6 @@ #include "sdram_ports_PINOUT_V1_IS42S16400F.h" -void sdram_server_PINOUT_V1_IS42S16400F(chanend client, struct sdram_ports_PINOUT_V1_IS42S16400F &ports); +void sdram_server_PINOUT_V1_IS42S16400F(chanend c_client, struct sdram_ports_PINOUT_V1_IS42S16400F &ports); #endif diff --git a/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.xc b/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.xc index 27a2667..44b1d58 100644 --- a/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.xc +++ b/module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.xc @@ -18,10 +18,11 @@ void sdram_init_PINOUT_V1_IS42S16400F(struct sdram_ports_PINOUT_V1_IS42S16400F & p.we <: 0; p.dq_ah <: 0; + sync(p.dq_ah); stop_clock(p.cb); T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; set_clock_div(p.cb, SDRAM_CLOCK_DIVIDER); set_port_clock(p.clk, p.cb); @@ -37,26 +38,28 @@ void sdram_init_PINOUT_V1_IS42S16400F(struct sdram_ports_PINOUT_V1_IS42S16400F & start_clock(p.cb); - p.dq_ah <: 0 @ t; + p.dq_ah @ t <: 0 ; t+=20; partout(p.cas,1, 0); partout(p.we, 1, 0); T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; p.dq_ah <: 0 @ t; + sync(p.dq_ah); + t+=20; partout_timed(p.ras,1, CTRL_RAS_NOP, t); partout_timed(p.cas,1, CTRL_CAS_NOP, t); partout_timed(p.we, 1, CTRL_WE_NOP, t); T :> time; - T when timerafter(t + 50 * TIMER_TICKS_PER_US) :> time; + T when timerafter(time + 50 * TIMER_TICKS_PER_US) :> time; p.dq_ah <: 0x04000400 @ t; - + sync(p.dq_ah); t+=60; partout_timed(p.ras, 2, CTRL_RAS_PRECHARGE | (CTRL_RAS_NOP<<1), t); @@ -71,15 +74,12 @@ void sdram_init_PINOUT_V1_IS42S16400F(struct sdram_ports_PINOUT_V1_IS42S16400F & // set mode register p.dq_ah @ t<: (SDRAM_MODE_REGISTER << 16)|SDRAM_MODE_REGISTER; - t+=32; - - //do 16 nops - t+=16; + sync(p.dq_ah); + t+=48; partout_timed(p.cas, 2, CTRL_CAS_LOAD_MODEREG | (CTRL_CAS_NOP<<1), t); partout_timed(p.ras, 2, CTRL_RAS_LOAD_MODEREG | (CTRL_RAS_NOP<<1), t); partout_timed(p.we, 2, CTRL_WE_LOAD_MODEREG | (CTRL_WE_NOP<<1), t); - } #if (SDRAM_CMDS_PER_REFRESH==2) @@ -122,18 +122,12 @@ void sdram_block_read_PINOUT_V1_IS42S16400F(unsigned buffer, unsigned word_count void sdram_short_block_read_PINOUT_V1_IS42S16400F(unsigned buffer, unsigned word_count, buffered port:32 dq, out buffered port:8 ctrl, unsigned term_time, unsigned st, out buffered port:32 ras); -/* - * These numbers are tuned for 50MIPS. - */ -//#define WRITE_SETUP_LATENCY (39) -//#define READ_SETUP_LATENCY (48) - /* * These numbers are tuned for 62.5MIPS. */ -#define WRITE_SETUP_LATENCY (50) -#define WRITE_COL_SETUP_LATENCY (50) -#define READ_SETUP_LATENCY (50) +#define WRITE_SETUP_LATENCY (80) +#define WRITE_COL_SETUP_LATENCY (80) +#define READ_SETUP_LATENCY (80) static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V1_IS42S16400F] = {(0<<13) | (0<<(13+16) | 1<<(10+16)), @@ -149,12 +143,12 @@ static inline void sdram_write_PINOUT_V1_IS42S16400F(unsigned row, unsigned col, unsigned jump; unsigned rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) + if(SDRAM_EXTERNAL_MEMORY_ACCESSOR){ if (col) col = col - 1; else col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16400F - 1); - + } rowcol = (col << 16) | row | bank_table[bank]; //adjust the buffer @@ -182,17 +176,17 @@ static inline void sdram_col_write_PINOUT_V1_IS42S16400F(unsigned bank, unsigned unsigned data_stop; unsigned rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) + if(SDRAM_EXTERNAL_MEMORY_ACCESSOR){ if (col) col = col - 1; else col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16400F - 1); - + } rowcol = (col << 16) | row | bank_table[bank]; data_stop = (0xffff << 16) | data; - t = partout_timestamped(ports.cas, 1, CTRL_WE_NOP); + t = partout_timestamped(ports.cas, 1, CTRL_CAS_NOP); - t += 50; + t += WRITE_COL_SETUP_LATENCY; partout_timed(ports.cas, 6, CTRL_CAS_ACTIVE | (CTRL_CAS_WRITE<<1) | (CTRL_CAS_NOP<<2) | (CTRL_CAS_TERM<<3) | (CTRL_CAS_PRECHARGE<<4) | (CTRL_CAS_NOP<<5), t); partout_timed(ports.ras, 6, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2) | (CTRL_RAS_TERM<<3) | (CTRL_RAS_PRECHARGE<<4) | (CTRL_RAS_NOP<<5), t); @@ -206,16 +200,16 @@ static inline void sdram_read_PINOUT_V1_IS42S16400F(unsigned row, unsigned col, unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V1_IS42S16400F &ports) { unsigned t, stop_time, jump, rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) + if(SDRAM_EXTERNAL_MEMORY_ACCESSOR){ if (col) col = col - 1; else col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16400F - 1); - + } rowcol = bank_table[bank] | (col << 16) | row; if (word_count < 4) { - t = partout_timestamped(ports.ras, 1, CTRL_WE_NOP); + t = partout_timestamped(ports.ras, 1, CTRL_RAS_NOP); t += READ_SETUP_LATENCY; stop_time = t + (4 << 1) + 4; @@ -229,7 +223,7 @@ static inline void sdram_read_PINOUT_V1_IS42S16400F(unsigned row, unsigned col, buffer -= 4 * (0x3f&(SDRAM_ROW_WORDS_PINOUT_V1_IS42S16400F - word_count)); jump = 2 * (SDRAM_ROW_WORDS_PINOUT_V1_IS42S16400F - word_count); - t = partout_timestamped(ports.ras, 1, CTRL_WE_NOP); + t = partout_timestamped(ports.ras, 1, CTRL_RAS_NOP); t+= READ_SETUP_LATENCY; stop_time = t + (word_count<<1)+4; diff --git a/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.h b/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.h index 40f1bc8..eefd6e6 100644 --- a/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.h +++ b/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.h @@ -3,6 +3,6 @@ #include "sdram_ports_PINOUT_V2_IS42S16400F.h" -void sdram_server_PINOUT_V2_IS42S16400F(chanend client, struct sdram_ports_PINOUT_V2_IS42S16400F &ports); +void sdram_server_PINOUT_V2_IS42S16400F(chanend c_client, struct sdram_ports_PINOUT_V2_IS42S16400F &ports); #endif diff --git a/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.xc b/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.xc index c6b27c4..0d0a66b 100644 --- a/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.xc +++ b/module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.xc @@ -15,11 +15,12 @@ void sdram_init_PINOUT_V2_IS42S16400F(struct sdram_ports_PINOUT_V2_IS42S16400F & p.ctrl <: 0; p.dq_ah <: 0; + sync(p.dq_ah); stop_clock(p.cb); T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; set_clock_div(p.cb, SDRAM_CLOCK_DIVIDER); set_port_clock(p.clk, p.cb); @@ -37,7 +38,7 @@ void sdram_init_PINOUT_V2_IS42S16400F(struct sdram_ports_PINOUT_V2_IS42S16400F & t+=20; T :> time; - T when timerafter(t + 100 * TIMER_TICKS_PER_US) :> time; + T when timerafter(time + 100 * TIMER_TICKS_PER_US) :> time; p.dq_ah <: 0 @ t; t+=20; @@ -60,10 +61,9 @@ void sdram_init_PINOUT_V2_IS42S16400F(struct sdram_ports_PINOUT_V2_IS42S16400F & // set mode register p.dq_ah @ t<: (SDRAM_MODE_REGISTER << 16)|SDRAM_MODE_REGISTER; - t+=32; - //do 16 nops - t+=16; + sync(p.dq_ah); + t+=48; partout_timed(p.ctrl, 8, CTRL_LOAD_MODEREG | (CTRL_NOP<<4), t); @@ -124,12 +124,12 @@ static inline void sdram_write_PINOUT_V2_IS42S16400F(unsigned row, unsigned col, unsigned jump; unsigned rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) - if (col) - col = col - 1; - else - col = (SDRAM_COL_COUNT_PINOUT_V2_IS42S16400F - 1); - + if(SDRAM_EXTERNAL_MEMORY_ACCESSOR){ + if (col) + col = col - 1; + else + col = (SDRAM_COL_COUNT_PINOUT_V2_IS42S16400F - 1); + } rowcol = (col << 16) | row | bank_table[bank]; //adjust the buffer @@ -157,12 +157,12 @@ static inline void sdram_col_write_PINOUT_V2_IS42S16400F(unsigned bank, unsigned unsigned data_stop; unsigned rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) - if (col) - col = col - 1; - else - col = (SDRAM_COL_COUNT_PINOUT_V2_IS42S16400F - 1); - + if(SDRAM_EXTERNAL_MEMORY_ACCESSOR){ + if (col) + col = col - 1; + else + col = (SDRAM_COL_COUNT_PINOUT_V2_IS42S16400F - 1); + } rowcol = (col << 16) | row | bank_table[bank]; data_stop = (0xffff << 16) | data; t = partout_timestamped(ports.ctrl, 4, CTRL_NOP); @@ -179,12 +179,12 @@ static inline void sdram_read_PINOUT_V2_IS42S16400F(unsigned row, unsigned col, unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V2_IS42S16400F &ports) { unsigned t, stop_time, jump, rowcol; - if(SDRAM_EXTERNAL_MEMORY_ACCESSOR) - if (col) - col = col - 1; - else - col = (SDRAM_COL_COUNT_PINOUT_V2_IS42S16400F - 1); - + if(SDRAM_EXTERNAL_MEMORY_ACCESSOR){ + if (col) + col = col - 1; + else + col = (SDRAM_COL_COUNT_PINOUT_V2_IS42S16400F - 1); + } rowcol = bank_table[bank] | (col << 16) | row; if (word_count < 4) { diff --git a/module_sdram/src/sdram.h b/module_sdram/src/sdram.h index b6ef1c1..4fc190b 100644 --- a/module_sdram/src/sdram.h +++ b/module_sdram/src/sdram.h @@ -14,7 +14,7 @@ * \param client The channel end connecting the application to the server * \param ports The structure carrying the SDRAM port details. */ -void sdram_server(chanend client, struct sdram_ports_PINOUT_V1_IS42S16400F &ports); +void sdram_server(chanend c_client, struct sdram_ports_PINOUT_V1_IS42S16400F &ports); #define sdram_server ADD_SUFFIX(sdram_server, SDRAM_DEFAULT_IMPLEMENTATION) @@ -24,14 +24,14 @@ void sdram_server(chanend client, struct sdram_ports_PINOUT_V1_IS42S16400F &por * \param buffer[] The buffer where the data was written or read from in the previous command. */ #pragma select handler -void sdram_wait_until_idle(chanend server, unsigned buffer[]); +void sdram_wait_until_idle(chanend c_server, unsigned buffer[]); /** \brief Function to wait until the SDRAM server is idle and ready to accept another command. * * \param server The channel end connecting the application to the server * \param buffer A pointer to the buffer where the data was written or read from in the previous command. */ -void sdram_wait_until_idle_p(chanend server, intptr_t buffer); +void sdram_wait_until_idle_p(chanend c_server, intptr_t buffer); /** \brief Used to read to an arbitrary size buffer of data from the SDRAM. * @@ -44,7 +44,7 @@ void sdram_wait_until_idle_p(chanend server, intptr_t buffer); * * Note: no buffer overrun checking is performed. */ -void sdram_buffer_read(chanend server, unsigned bank, unsigned start_row, +void sdram_buffer_read(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, unsigned buffer[]); /** \brief Used to read to an arbitrary size buffer of data from the SDRAM. @@ -58,7 +58,7 @@ void sdram_buffer_read(chanend server, unsigned bank, unsigned start_row, * * Note: no buffer overrun checking is performed. */ -void sdram_buffer_read_p(chanend server, unsigned bank, unsigned start_row, +void sdram_buffer_read_p(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, intptr_t buffer); /** \brief Used to write an arbitrary sized buffer of data to the SDRAM. @@ -72,7 +72,7 @@ void sdram_buffer_read_p(chanend server, unsigned bank, unsigned start_row, * * Note: no buffer overrun checking is performed. */ -void sdram_buffer_write(chanend server, unsigned bank, unsigned start_row, +void sdram_buffer_write(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, unsigned buffer[]); /** \brief Used to write an arbitrary sized buffer of data to the SDRAM. @@ -86,7 +86,7 @@ void sdram_buffer_write(chanend server, unsigned bank, unsigned start_row, * * Note: no buffer overrun checking is performed. */ -void sdram_buffer_write_p(chanend server, unsigned bank, unsigned start_row, +void sdram_buffer_write_p(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, intptr_t buffer); /** \brief Used read a full row of data from a buffer to the SDRAM @@ -99,7 +99,7 @@ void sdram_buffer_write_p(chanend server, unsigned bank, unsigned start_row, * Note: no buffer overrun checking is performed. * Full row accesses are always begin aligned to coloumn 0. */ -void sdram_full_row_read(chanend server, unsigned bank, unsigned row, +void sdram_full_row_read(chanend c_server, unsigned bank, unsigned row, unsigned buffer[]); /** \brief Used read a full row of data from a buffer to the SDRAM @@ -112,7 +112,7 @@ void sdram_full_row_read(chanend server, unsigned bank, unsigned row, * Note: no buffer overrun checking is performed. * Full row accesses are always begin aligned to coloumn 0. */ -void sdram_full_row_read_p(chanend server, unsigned bank, unsigned row, +void sdram_full_row_read_p(chanend c_server, unsigned bank, unsigned row, intptr_t buffer); /** \brief Used write a full row of data from a buffer to the SDRAM @@ -125,7 +125,7 @@ void sdram_full_row_read_p(chanend server, unsigned bank, unsigned row, * Note: no buffer overrun checking is performed. * Full row accesses are always begin aligned to coloumn 0. */ -void sdram_full_row_write(chanend server, unsigned bank, unsigned row, +void sdram_full_row_write(chanend c_server, unsigned bank, unsigned row, unsigned buffer[]); /** \brief Used write a full row of data from a buffer to the SDRAM @@ -138,7 +138,7 @@ void sdram_full_row_write(chanend server, unsigned bank, unsigned row, * Note: no buffer overrun checking is performed. * Full row accesses are always begin aligned to coloumn 0. */ -void sdram_full_row_write_p(chanend server, unsigned bank, unsigned row, +void sdram_full_row_write_p(chanend c_server, unsigned bank, unsigned row, intptr_t buffer); /** \brief Used write a single column of data to the SDRAM @@ -150,5 +150,13 @@ void sdram_full_row_write_p(chanend server, unsigned bank, unsigned row, * \param data A short of data to write to the SDRAM. * */ -void sdram_col_write(chanend server, unsigned bank, unsigned row, unsigned col, short data); +void sdram_col_write(chanend c_server, unsigned bank, unsigned row, unsigned col, short data); + +/** \brief Shutdown the SDRAM server. + * + * \param server The channel end connecting the application to the server + * + */ +void sdram_shutdown(chanend c_server); + #endif diff --git a/module_sdram/src/sdram_client.xc b/module_sdram/src/sdram_client.xc index 4dac732..e7a94e2 100644 --- a/module_sdram/src/sdram_client.xc +++ b/module_sdram/src/sdram_client.xc @@ -2,96 +2,100 @@ #include "sdram.h" #if (SDRAM_ENABLE_CMD_BUFFER_READ) -void sdram_buffer_read_p(chanend server, unsigned bank, unsigned start_row, unsigned start_col, +void sdram_buffer_read_p(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, intptr_t buffer) { - server <: (char)SDRAM_CMD_BUFFER_READ; + c_server <: (char)SDRAM_CMD_BUFFER_READ; master { - server <: bank; - server <: start_row; - server <: start_col; - server <: width_words; - server <: buffer; + c_server <: bank; + c_server <: start_row; + c_server <: start_col; + c_server <: width_words; + c_server <: buffer; } } -void sdram_buffer_read(chanend server, unsigned bank, unsigned start_row, unsigned start_col, +void sdram_buffer_read(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, unsigned buffer[]) { intptr_t buffer_pointer; asm("mov %0, %1" : "=r"(buffer_pointer) : "r"(buffer)); - sdram_buffer_read_p( server, bank, start_row, start_col, width_words, buffer_pointer); + sdram_buffer_read_p( c_server, bank, start_row, start_col, width_words, buffer_pointer); } #endif #if (SDRAM_ENABLE_CMD_BUFFER_WRITE) -void sdram_buffer_write_p(chanend server, unsigned bank, unsigned start_row, unsigned start_col, +void sdram_buffer_write_p(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, intptr_t buffer) { - server <: (char)SDRAM_CMD_BUFFER_WRITE; + c_server <: (char)SDRAM_CMD_BUFFER_WRITE; master { - server <: bank; - server <: start_row; - server <: start_col; - server <: width_words; - server <: buffer; + c_server <: bank; + c_server <: start_row; + c_server <: start_col; + c_server <: width_words; + c_server <: buffer; } } -void sdram_buffer_write(chanend server, unsigned bank, unsigned start_row, unsigned start_col, +void sdram_buffer_write(chanend c_server, unsigned bank, unsigned start_row, unsigned start_col, unsigned width_words, unsigned buffer[]){ intptr_t buffer_pointer; asm("mov %0, %1" : "=r"(buffer_pointer) : "r"(buffer)); - sdram_buffer_write_p( server, bank, start_row, start_col, width_words, buffer_pointer); + sdram_buffer_write_p( c_server, bank, start_row, start_col, width_words, buffer_pointer); } #endif #if (SDRAM_ENABLE_CMD_FULL_ROW_READ) -void sdram_full_row_read_p(chanend server, unsigned bank, unsigned start_row, intptr_t buffer) { - server <: (char)SDRAM_CMD_FULL_ROW_READ; +void sdram_full_row_read_p(chanend c_server, unsigned bank, unsigned start_row, intptr_t buffer) { + c_server <: (char)SDRAM_CMD_FULL_ROW_READ; master { - server <: bank; - server <: start_row; - server <: buffer; + c_server <: bank; + c_server <: start_row; + c_server <: buffer; } } -void sdram_full_row_read(chanend server, unsigned bank, unsigned start_row, unsigned buffer[]) { +void sdram_full_row_read(chanend c_server, unsigned bank, unsigned start_row, unsigned buffer[]) { intptr_t buffer_pointer; asm("mov %0, %1" : "=r"(buffer_pointer) : "r"(buffer)); - sdram_full_row_read_p(server, bank, start_row, buffer_pointer); + sdram_full_row_read_p(c_server, bank, start_row, buffer_pointer); } #endif #if (SDRAM_ENABLE_CMD_FULL_ROW_WRITE) -void sdram_full_row_write_p(chanend server, unsigned bank, unsigned start_row, intptr_t buffer) { - server <: (char)SDRAM_CMD_FULL_ROW_WRITE; +void sdram_full_row_write_p(chanend c_server, unsigned bank, unsigned start_row, intptr_t buffer) { + c_server <: (char)SDRAM_CMD_FULL_ROW_WRITE; master { - server <: bank; - server <: start_row; - server <: buffer; + c_server <: bank; + c_server <: start_row; + c_server <: buffer; } } -void sdram_full_row_write(chanend server, unsigned bank, unsigned start_row, unsigned buffer[]) { +void sdram_full_row_write(chanend c_server, unsigned bank, unsigned start_row, unsigned buffer[]) { intptr_t buffer_pointer; asm("mov %0, %1" : "=r"(buffer_pointer) : "r"(buffer)); - sdram_full_row_write_p(server, bank, start_row, buffer_pointer); + sdram_full_row_write_p(c_server, bank, start_row, buffer_pointer); } #endif #if (SDRAM_ENABLE_CMD_COL_WRITE) -void sdram_col_write(chanend server, unsigned bank, unsigned row, unsigned col, short data) { - server <: (char)SDRAM_CMD_COL_WRITE; +void sdram_col_write(chanend c_server, unsigned bank, unsigned row, unsigned col, short data) { + c_server <: (char)SDRAM_CMD_COL_WRITE; master { - server <: bank; - server <: row; - server <: col; - server <: data; + c_server <: bank; + c_server <: row; + c_server <: col; + c_server <: data; } } #endif -void sdram_wait_until_idle_p(chanend server, intptr_t buffer) { - chkct(server, XS1_CT_END); +void sdram_shutdown(chanend c_server){ + c_server <: (char)SDRAM_CMD_SHUTDOWN; } -void sdram_wait_until_idle(chanend server, unsigned buffer[]) { - chkct(server, XS1_CT_END); + +void sdram_wait_until_idle_p(chanend c_server, intptr_t buffer) { + chkct(c_server, XS1_CT_END); +} +void sdram_wait_until_idle(chanend c_server, unsigned buffer[]) { + chkct(c_server, XS1_CT_END); } diff --git a/module_sdram/src/sdram_commands.h b/module_sdram/src/sdram_commands.h index 9231f5a..0691f45 100644 --- a/module_sdram/src/sdram_commands.h +++ b/module_sdram/src/sdram_commands.h @@ -22,7 +22,8 @@ enum { SDRAM_CMD_BUFFER_WRITE, SDRAM_CMD_FULL_ROW_READ, SDRAM_CMD_FULL_ROW_WRITE, - SDRAM_CMD_COL_WRITE + SDRAM_CMD_COL_WRITE, + SDRAM_CMD_SHUTDOWN }; /* diff --git a/module_sdram/src/sdram_server_common.inc b/module_sdram/src/sdram_server_common.inc index 95599af..890cb2e 100644 --- a/module_sdram/src/sdram_server_common.inc +++ b/module_sdram/src/sdram_server_common.inc @@ -58,17 +58,17 @@ static void write_buffer(unsigned start_row, unsigned start_col, } } -static void handle_command(char cmd, chanend client, struct ADD_SUFFIX(sdram_ports,CUR_IMPL) &ports) { +static int handle_command(char cmd, chanend c_client, struct ADD_SUFFIX(sdram_ports,CUR_IMPL) &ports) { switch (cmd) { #if (SDRAM_ENABLE_CMD_BUFFER_READ==1) case SDRAM_CMD_BUFFER_READ: { unsigned bank, start_row, start_col, width_words, pointer; slave { - client :> bank; - client :> start_row; - client :> start_col; - client :> width_words; - client :> pointer; + c_client :> bank; + c_client :> start_row; + c_client :> start_col; + c_client :> width_words; + c_client :> pointer; } read_buffer(start_row, start_col, bank, pointer, width_words, ports); break; @@ -78,11 +78,11 @@ static void handle_command(char cmd, chanend client, struct ADD_SUFFIX(sdram_por case SDRAM_CMD_BUFFER_WRITE: { unsigned bank, start_row, start_col, width_words, pointer; slave { - client :> bank; - client :> start_row; - client :> start_col; - client :> width_words; - client :> pointer; + c_client :> bank; + c_client :> start_row; + c_client :> start_col; + c_client :> width_words; + c_client :> pointer; } write_buffer(start_row, start_col, bank, pointer, width_words, ports); break; @@ -92,9 +92,9 @@ static void handle_command(char cmd, chanend client, struct ADD_SUFFIX(sdram_por case SDRAM_CMD_FULL_ROW_WRITE: { unsigned bank, start_row, pointer; slave { - client :> bank; - client :> start_row; - client :> pointer; + c_client :> bank; + c_client :> start_row; + c_client :> pointer; } ADD_SUFFIX(sdram_write,CUR_IMPL)(start_row, 0, bank, pointer, ADD_SUFFIX(SDRAM_ROW_WORDS,CUR_IMPL), ports); break; @@ -104,9 +104,9 @@ static void handle_command(char cmd, chanend client, struct ADD_SUFFIX(sdram_por case SDRAM_CMD_FULL_ROW_READ: { unsigned bank, start_row, pointer; slave { - client :> bank; - client :> start_row; - client :> pointer; + c_client :> bank; + c_client :> start_row; + c_client :> pointer; } ADD_SUFFIX(sdram_read,CUR_IMPL)(start_row, 0, bank, pointer, ADD_SUFFIX(SDRAM_ROW_WORDS,CUR_IMPL), ports); break; @@ -117,27 +117,32 @@ static void handle_command(char cmd, chanend client, struct ADD_SUFFIX(sdram_por unsigned bank, row, col; short data; slave { - client :> bank; - client :> row; - client :> col; - client :> data; + c_client :> bank; + c_client :> row; + c_client :> col; + c_client :> data; } ADD_SUFFIX(sdram_col_write,CUR_IMPL)(bank, row, col, data, ports); break; } #endif + case SDRAM_CMD_SHUTDOWN: { + return 1; + } + default: #if (XCC_VERSION_MAJOR >= 12) __builtin_unreachable(); #endif break; } + return 0; } #define SDRAM_REF_TICKS_PER_REFRESH ((XCORE_TIMER_TICKS_PER_MS*SDRAM_REFRESH_MS)/SDRAM_REFRESH_CYCLES) #define XCORE_TIMER_TICKS_PER_MS 100000 -void ADD_SUFFIX(sdram_server,CUR_IMPL)(chanend client, struct ADD_SUFFIX(sdram_ports,CUR_IMPL) &ports) { +void ADD_SUFFIX(sdram_server,CUR_IMPL)(chanend c_client, struct ADD_SUFFIX(sdram_ports,CUR_IMPL) &ports) { unsigned T, now, then; ADD_SUFFIX(sdram_init,CUR_IMPL)(ports); @@ -157,9 +162,11 @@ void ADD_SUFFIX(sdram_server,CUR_IMPL)(chanend client, struct ADD_SUFFIX(sdram_p T = then + SDRAM_REF_TICKS_PER_REFRESH * SDRAM_ACCEPTABLE_REFRESH_GAP; break; } - case client :> char cmd: { - handle_command(cmd, client, ports); - outct(client, XS1_CT_END); + case c_client :> char cmd: { + if(!handle_command(cmd, c_client, ports)) + outct(c_client, XS1_CT_END); + else + return; break; } } diff --git a/module_sdram_memory_mapper/.cproject b/module_sdram_memory_mapper/.cproject index 8530a61..a9865ec 100644 --- a/module_sdram_memory_mapper/.cproject +++ b/module_sdram_memory_mapper/.cproject @@ -1,4 +1,4 @@ - + @@ -153,23 +153,264 @@ - diff --git a/module_sdram_memory_mapper/src/sdram_memory_mapper.h b/module_sdram_memory_mapper/src/sdram_memory_mapper.h index b5d1391..65e2220 100644 --- a/module_sdram_memory_mapper/src/sdram_memory_mapper.h +++ b/module_sdram_memory_mapper/src/sdram_memory_mapper.h @@ -8,7 +8,7 @@ * \param words The count of words to be read * \param buffer[] The buffer where the data will be written to. */ -void mm_read_words(chanend server, unsigned address, unsigned words, unsigned buffer[]); +void mm_read_words(chanend c_server, unsigned address, unsigned words, unsigned buffer[]); /** \brief Reads words from the SDRAM server on the end of the channel provided. * @@ -17,7 +17,7 @@ void mm_read_words(chanend server, unsigned address, unsigned words, unsigned bu * \param words The count of words to be read * \param buffer A pointer to the buffer where the data will be written to. */ -void mm_read_words_p(chanend server, unsigned address, unsigned words, intptr_t buffer); +void mm_read_words_p(chanend c_server, unsigned address, unsigned words, intptr_t buffer); /** Writes words to the SDRAM server on the end of the channel provided. * @@ -26,7 +26,7 @@ void mm_read_words_p(chanend server, unsigned address, unsigned words, intptr_t * \param words The count of words to be written. * \param buffer[] The buffer where the data will be written to. */ -void mm_write_words(chanend server, unsigned address, unsigned words, unsigned buffer[]); +void mm_write_words(chanend c_server, unsigned address, unsigned words, unsigned buffer[]); /** Writes words to the SDRAM server on the end of the channel provided. * @@ -35,20 +35,20 @@ void mm_write_words(chanend server, unsigned address, unsigned words, unsigned b * \param words The count of words to be written. * \param buffer A pointer to the buffer where the data will be written to. */ -void mm_write_words_p(chanend server, unsigned address, unsigned words, intptr_t buffer); +void mm_write_words_p(chanend c_server, unsigned address, unsigned words, intptr_t buffer); /** Returns when the SDRAM server is in the idle state. * * \param server The channel end connecting to the SDRAM server. * \param buffer[] The buffer which the last command was performed on. */ -void mm_wait_until_idle(chanend server, unsigned buffer[]); +void mm_wait_until_idle(chanend c_server, unsigned buffer[]); /** Returns when the SDRAM server is in the idle state. * * \param server The channel end connecting to the SDRAM server. * \param buffer A pointer to the buffer which the last command was performed on. */ -void mm_wait_until_idle_p(chanend server, intptr_t buffer); +void mm_wait_until_idle_p(chanend c_server, intptr_t buffer); #endif /* MODULE_MEMORY_MAPPER_H_ */ diff --git a/module_sdram_memory_mapper/src/sdram_memory_mapper.xc b/module_sdram_memory_mapper/src/sdram_memory_mapper.xc index 2fa1db5..3298791 100644 --- a/module_sdram_memory_mapper/src/sdram_memory_mapper.xc +++ b/module_sdram_memory_mapper/src/sdram_memory_mapper.xc @@ -6,36 +6,36 @@ * */ -void mm_read_words_p(chanend server, unsigned address, unsigned words, intptr_t buffer){ +void mm_read_words_p(chanend c_server, unsigned address, unsigned words, intptr_t buffer){ unsigned bank = address >> (SDRAM_ROW_ADDRESS_BITS + SDRAM_COL_ADDRESS_BITS+1) & ((1<> (SDRAM_COL_ADDRESS_BITS) & ((1<> (SDRAM_ROW_ADDRESS_BITS + SDRAM_COL_ADDRESS_BITS+1) & ((1<> (SDRAM_COL_ADDRESS_BITS) & ((1< + + XA-SK-SDRAM + SDRAM + memory + XA-SK-SDRAM module_sdram @@ -8,35 +13,36 @@ Memory SDRAM - - XA-SK-SDRAM - module_sdram - SDRAM - memory - - + XA-SK-SDRAM module_sdram module_slicekit_support Memory SDRAM - + XA-SK-SDRAM module_sdram module_slicekit_support Memory SDRAM - + XA-SK-SDRAM + module_sdram SDRAM memory - 3f82b846395c07e8dd32ad9951afc209b6ed7efc + d0531d7c68ab67334582c324828e36d617baf8b3 git@github.com:xcore/sc_util + 1.0.3rc0 + + + 7920fc4235a96585274d73d25d275ea63b4cd285 + https://github.com/xcore/sc_slicekit_support.git + 1.0.3rc0 Various modules related to controlling external sdram app_sdram_demo/doc_quickstart @@ -54,7 +60,7 @@ - + XM-001915-SM XMOS sc_sdram_burst.git