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added new target plus asm fixes

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1 parent f0821a9 commit b6a801ca5c56319c9598f271cbfcfefd98b1bb1e @andrewstanfordjason andrewstanfordjason committed Nov 26, 2012
Showing with 2,520 additions and 2,649 deletions.
  1. +13 −0 CHANGELOG.rst
  2. +399 −877 app_sdram_benchmark/.cproject
  3. +1 −2 app_sdram_benchmark/.project
  4. +399 −877 app_sdram_demo/.cproject
  5. +1 −2 app_sdram_demo/.project
  6. +405 −877 app_sdram_regress/.cproject
  7. +5 −2 app_sdram_regress/.project
  8. +7 −0 doc/api.rst
  9. +3 −0 doc/programming.rst
  10. +2 −2 module_sdram/.cproject
  11. +6 −4 module_sdram/src/PINOUT_V0/sdram_io_PINOUT_V0.S
  12. +28 −0 module_sdram/src/PINOUT_V0/sdram_server_PINOUT_V0.xc
  13. +6 −0 module_sdram/src/PINOUT_V1_IS42S16160D/sdram_io_PINOUT_V1_IS42S16160D.S
  14. +27 −0 module_sdram/src/PINOUT_V1_IS42S16160D/sdram_server_PINOUT_V1_IS42S16160D.xc
  15. +8 −0 module_sdram/src/PINOUT_V1_IS42S16400F/sdram_io_PINOUT_V1_IS42S16400F.S
  16. +27 −0 module_sdram/src/PINOUT_V1_IS42S16400F/sdram_server_PINOUT_V1_IS42S16400F.xc
  17. +251 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_block_read_body_PINOUT_V2_IS42S16400F.inc
  18. +256 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_block_write_body_PINOUT_V2_IS42S16400F.inc
  19. +80 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_config_PINOUT_V2_IS42S16400F.h
  20. +31 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_geometry_PINOUT_V2_IS42S16400F.h
  21. +235 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_io_PINOUT_V2_IS42S16400F.S
  22. +21 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_ports_PINOUT_V2_IS42S16400F.h
  23. +8 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.h
  24. +216 −0 module_sdram/src/PINOUT_V2_IS42S16400F/sdram_server_PINOUT_V2_IS42S16400F.xc
  25. +12 −0 module_sdram/src/sdram.h
  26. +12 −0 module_sdram/src/sdram_client.xc
  27. +18 −1 module_sdram/src/sdram_commands.h
  28. +24 −3 module_sdram/src/sdram_control.h
  29. +1 −0 module_sdram/src/sdram_geometry.h
  30. +1 −0 module_sdram/src/sdram_ports.h
  31. +15 −0 module_sdram/src/sdram_server_common.inc
  32. +2 −2 module_sdram_memory_mapper/.cproject
View
@@ -1,6 +1,19 @@
sc_sdram_burst Change Log
=========================
+1.0.4
+-----
+ * Extended control defines to work for 4 bit ports in an arbitrary way
+
+1.0.3
+-----
+ * Added PINOUT_V2_IS42S16400F target
+ * Added cc_tops and bottoms to all the assembly for elimination if unused
+
+1.0.2
+-----
+ * Added sdram_col_write() for writing to a single column quickly
+
1.0.1
-----
* Minor fix to demo apps (declare port structures on the correct tile)
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@@ -21,7 +21,7 @@
<arguments>
<dictionary>
<key>?children?</key>
- <value>?name?=outputEntries\|?children?=?name?=entry\\\\|\\|\||</value>
+ <value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
</dictionary>
<dictionary>
<key>?name?</key>
@@ -83,4 +83,3 @@
<nature>com.xmos.cdt.core.XdeProjectNature</nature>
</natures>
</projectDescription>
-
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@@ -21,7 +21,7 @@
<arguments>
<dictionary>
<key>?children?</key>
- <value>?name?=outputEntries\|?children?=?name?=entry\\\\|\\|\||</value>
+ <value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
</dictionary>
<dictionary>
<key>?name?</key>
@@ -83,4 +83,3 @@
<nature>com.xmos.cdt.core.XdeProjectNature</nature>
</natures>
</projectDescription>
-
View

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@@ -21,7 +21,7 @@
<arguments>
<dictionary>
<key>?children?</key>
- <value>?name?=outputEntries\|?children?=?name?=entry\\\\|\\|\||</value>
+ <value>?name?=outputEntries\|?children?=?name?=entry\\\\\\\|\\\|\||</value>
</dictionary>
<dictionary>
<key>?name?</key>
@@ -60,6 +60,10 @@
<value>true</value>
</dictionary>
<dictionary>
+ <key>org.eclipse.cdt.make.core.environment</key>
+ <value>XTA_ENABLED=true|</value>
+ </dictionary>
+ <dictionary>
<key>org.eclipse.cdt.make.core.stopOnError</key>
<value>true</value>
</dictionary>
@@ -83,4 +87,3 @@
<nature>com.xmos.cdt.core.XdeProjectNature</nature>
</natures>
</projectDescription>
-
View
@@ -85,6 +85,9 @@ These are non-implementation specific.
**SDRAM_ENABLE_CMD_FULL_ROW_WRITE**
Enable/Disable the full row write command.
+**SDRAM_ENABLE_CMD_COL_WRITE**
+ Enable/Disable the col write command.
+
These defines switch commands on and off in the server and client. Set to 0 for disable, set to 1 for enable. Disabling unused commands will cause a code size decrease.
Port Config
@@ -119,6 +122,10 @@ C Interface
.. doxygenfunction:: sdram_buffer_read_p
.. doxygenfunction:: sdram_full_row_read_p
+C and XC Interface
+------------------
+.. doxygenfunction:: sdram_col_write
+
SDRAM Memory Mapper API
-----------------------
View
@@ -7,10 +7,13 @@ This section provides information on how to program applications using the SDRAM
SDRAM Default implementation
----------------------------
For convenience the ``module_sdram`` can use a default implementation. When the define ``SDRAM_DEFAULT_IMPLEMENTATION`` is set in ``sdram_conf.h`` to one of the supported targets then the ``sdram_server`` function will act as a call to the specified implementation. The same applies for the ``sdram_ports`` structure. The currently supported targets are:
+ * PINOUT_V2_IS42S16400F - This corresponds to the ISSI part IS42S16400F in a 21 pin configuration.
* PINOUT_V1_IS42S16400F - This corresponds to the ISSI part IS42S16400F in a 20 pin configuration.
* PINOUT_V1_IS42S16160D - This corresponds to the ISSI part IS42S16160D in a 20 pin configuration.
* PINOUT_V0 - This is for a legacy 22 pin configuration.
+See the individual ``port.h`` files to find the port configurations.
+
Single SDRAM Support
--------------------
View
@@ -153,8 +153,8 @@
<listOptionValue builtIn="false" value="__EXCEPTIONS=1"/>
<listOptionValue builtIn="false" value="__WCHAR_UNSIGNED__=1"/>
</option>
- <option id="com.xmos.c.compiler.option.include.paths.66972520" name="com.xmos.c.compiler.option.include.paths" superClass="com.xmos.c.compiler.option.include.paths" valueType="includePath"/>
- <option id="gnu.c.compiler.option.include.paths.11690773" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths" valueType="includePath"/>
+ <option id="com.xmos.c.compiler.option.include.paths.66972520" name="com.xmos.c.compiler.option.include.paths" superClass="com.xmos.c.compiler.option.include.paths"/>
+ <option id="gnu.c.compiler.option.include.paths.11690773" name="Include paths (-I)" superClass="gnu.c.compiler.option.include.paths"/>
<option id="com.xmos.xc.compiler.option.include.paths.108304261" name="com.xmos.xc.compiler.option.include.paths" superClass="com.xmos.xc.compiler.option.include.paths" valueType="includePath">
<listOptionValue builtIn="false" value="&quot;${XMOS_DOC_PATH}/../target/include&quot;"/>
<listOptionValue builtIn="false" value="&quot;${XMOS_DOC_PATH}/../target/include/gcc&quot;"/>
@@ -1,9 +1,6 @@
-.section .cp.const4, "acM", @progbits, 4
+.cc_top sdram_block_write_PINOUT_V0.function
.align 4
-burst_term:
-.word 0xeeee4eec
-
.text
#define MAX_BUF_READ_SIZE (128)
.align 4
@@ -58,7 +55,9 @@ sdram_block_write_PINOUT_V0:
retsp 0
.globl sdram_block_write_PINOUT_V0.nstackwords
.linkset sdram_block_write_PINOUT_V0.nstackwords, 1
+.cc_bottom sdram_block_write_PINOUT_V0.function
+.cc_top sdram_block_read_PINOUT_V0.function
.align 4
.globl sdram_block_read_PINOUT_V0
.type sdram_block_read_PINOUT_V0, @function
@@ -157,6 +156,8 @@ jump:
.globl sdram_block_read_PINOUT_V0.nstackwords
.linkset sdram_block_read_PINOUT_V0.nstackwords, 5
+.cc_bottom sdram_block_read_PINOUT_V0.function
+.cc_top sdram_short_block_read_PINOUT_V0.function
.align 4
.globl sdram_short_block_read_PINOUT_V0
.type sdram_short_block_read_PINOUT_V0, @function
@@ -228,3 +229,4 @@ sdram_short_block_read_PINOUT_V0:
.globl sdram_short_block_read_PINOUT_V0.nstackwords
.linkset sdram_short_block_read_PINOUT_V0.nstackwords, 4
+.cc_bottom sdram_short_block_read_PINOUT_V0.function
@@ -116,6 +116,7 @@ void sdram_short_block_read_PINOUT_V0(unsigned buffer, unsigned word_count, out
* These numbers are tuned for 50MIPS.
*/
#define WRITE_SETUP_LATENCY (50)
+#define WRITE_COL_SETUP_LATENCY (50)
#define READ_SETUP_LATENCY (50)
static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V0] =
@@ -164,6 +165,33 @@ static inline void sdram_write_PINOUT_V0(unsigned row, unsigned col, unsigned ba
}
#pragma unsafe arrays
+static inline void sdram_col_write_PINOUT_V0(unsigned bank, unsigned row, unsigned col,
+ short data, struct sdram_ports_PINOUT_V0 &ports) {
+ unsigned t;
+ unsigned data_stop;
+ unsigned rowcol;
+
+ if(SDRAM_EXTERNAL_MEMORY_ACCESSOR)
+ if (col)
+ col = col - 1;
+ else
+ col = (SDRAM_COL_COUNT_PINOUT_V0 - 1);
+
+ rowcol = (col << 16) | row | bank_table[bank];
+ data_stop = (data << 16) | 0xffff;
+ t = partout_timestamped(ports.cas, 1, CTRL_WE_NOP);
+
+ t += WRITE_COL_SETUP_LATENCY;
+
+ partout_timed(ports.cas, 6, CTRL_CAS_ACTIVE | (CTRL_CAS_WRITE<<1) | (CTRL_CAS_NOP<<2) | (CTRL_CAS_TERM<<3) | (CTRL_CAS_PRECHARGE<<4) | (CTRL_CAS_NOP<<5), t);
+ partout_timed(ports.ras, 6, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2) | (CTRL_RAS_TERM<<3) | (CTRL_RAS_PRECHARGE<<4) | (CTRL_RAS_NOP<<5), t);
+ partout_timed(ports.we , 6, CTRL_WE_ACTIVE | (CTRL_WE_WRITE<<1) | (CTRL_WE_NOP<<2) | (CTRL_WE_TERM<<3) | (CTRL_WE_PRECHARGE<<4) | (CTRL_WE_NOP<<5) , t);
+ ports.dqm @ t <: 0x2;
+ ports.dq_ah @ t<: rowcol;
+ ports.dq_ah <: data_stop;
+}
+
+#pragma unsafe arrays
static inline void sdram_read_PINOUT_V0(unsigned row, unsigned col, unsigned bank,
unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V0 &ports) {
@@ -1,4 +1,5 @@
.text
+.cc_top sdram_block_write_PINOUT_V1_IS42S16160D.function
.align 4
.globl sdram_block_write_PINOUT_V1_IS42S16160D
.type sdram_block_write_PINOUT_V1_IS42S16160D, @function
@@ -58,7 +59,9 @@ sdram_block_write_PINOUT_V1_IS42S16160D:
.linkset sdram_block_write_PINOUT_V1_IS42S16160D.maxchanends, 0
.globl sdram_block_write_PINOUT_V1_IS42S16160D.maxthreads
.linkset sdram_block_write_PINOUT_V1_IS42S16160D.maxthreads, 1
+.cc_bottom sdram_block_write_PINOUT_V1_IS42S16160D.function
+.cc_top sdram_block_read_PINOUT_V1_IS42S16160D.function
.align 4
.globl sdram_block_read_PINOUT_V1_IS42S16160D
.type sdram_block_read_PINOUT_V1_IS42S16160D, @function
@@ -164,6 +167,8 @@ jump:
.globl sdram_block_read_PINOUT_V1_IS42S16160D.maxthreads
.linkset sdram_block_read_PINOUT_V1_IS42S16160D.maxthreads, 1
+.cc_bottom sdram_block_read_PINOUT_V1_IS42S16160D.function
+.cc_top sdram_short_block_read_PINOUT_V1_IS42S16160D.function
.align 4
.globl sdram_short_block_read_PINOUT_V1_IS42S16160D
.type sdram_short_block_read_PINOUT_V1_IS42S16160D, @function
@@ -241,3 +246,4 @@ sdram_short_block_read_PINOUT_V1_IS42S16160D:
.globl sdram_short_block_read_PINOUT_V1_IS42S16160D.maxthreads
.linkset sdram_short_block_read_PINOUT_V1_IS42S16160D.maxthreads, 1
+.cc_bottom sdram_short_block_read_PINOUT_V1_IS42S16160D.function
@@ -122,6 +122,7 @@ void sdram_short_block_read_PINOUT_V1_IS42S16160D(unsigned buffer, unsigned word
* These numbers are tuned for 50MIPS.
*/
#define WRITE_SETUP_LATENCY (80)
+#define WRITE_COL_SETUP_LATENCY (80)
#define READ_SETUP_LATENCY (80)
static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V1_IS42S16160D] =
@@ -176,6 +177,32 @@ static inline void sdram_write_PINOUT_V1_IS42S16160D(unsigned row, unsigned col,
}
#pragma unsafe arrays
+static inline void sdram_col_write_PINOUT_V1_IS42S16160D(unsigned bank, unsigned row, unsigned col,
+ short data, struct sdram_ports_PINOUT_V1_IS42S16160D &ports) {
+ unsigned t;
+ unsigned data_stop;
+ unsigned rowcol;
+
+ if(SDRAM_EXTERNAL_MEMORY_ACCESSOR)
+ if (col)
+ col = col - 1;
+ else
+ col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16160D - 1);
+
+ rowcol = (col << 16) | row | bank_table[bank];
+ data_stop = (data << 16) | 0xffff;
+ t = partout_timestamped(ports.cas, 1, CTRL_WE_NOP);
+
+ t += WRITE_COL_SETUP_LATENCY;
+
+ partout_timed(ports.cas, 6, CTRL_CAS_ACTIVE | (CTRL_CAS_WRITE<<1) | (CTRL_CAS_NOP<<2) | (CTRL_CAS_TERM<<3) | (CTRL_CAS_PRECHARGE<<4) | (CTRL_CAS_NOP<<5), t);
+ partout_timed(ports.ras, 6, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2) | (CTRL_RAS_TERM<<3) | (CTRL_RAS_PRECHARGE<<4) | (CTRL_RAS_NOP<<5), t);
+ partout_timed(ports.we , 6, CTRL_WE_ACTIVE | (CTRL_WE_WRITE<<1) | (CTRL_WE_NOP<<2) | (CTRL_WE_TERM<<3) | (CTRL_WE_PRECHARGE<<4) | (CTRL_WE_NOP<<5) , t);
+ ports.dq_ah @ t<: rowcol;
+ ports.dq_ah <: data_stop;
+}
+
+#pragma unsafe arrays
static inline void sdram_read_PINOUT_V1_IS42S16160D(unsigned row, unsigned col, unsigned bank,
unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V1_IS42S16160D &ports) {
unsigned t, stop_time, jump, rowcol;
@@ -1,4 +1,5 @@
.text
+.cc_top sdram_block_write_PINOUT_V1_IS42S16400F.function
.align 4
.globl sdram_block_write_PINOUT_V1_IS42S16400F
.type sdram_block_write_PINOUT_V1_IS42S16400F, @function
@@ -58,7 +59,10 @@ sdram_block_write_PINOUT_V1_IS42S16400F:
.linkset sdram_block_write_PINOUT_V1_IS42S16400F.maxchanends, 0
.globl sdram_block_write_PINOUT_V1_IS42S16400F.maxthreads
.linkset sdram_block_write_PINOUT_V1_IS42S16400F.maxthreads, 1
+.cc_bottom sdram_block_write_PINOUT_V1_IS42S16400F.function
+
+.cc_top sdram_block_read_PINOUT_V1_IS42S16400F.function
.align 4
.globl sdram_block_read_PINOUT_V1_IS42S16400F
.type sdram_block_read_PINOUT_V1_IS42S16400F, @function
@@ -164,6 +168,9 @@ jump:
.globl sdram_block_read_PINOUT_V1_IS42S16400F.maxthreads
.linkset sdram_block_read_PINOUT_V1_IS42S16400F.maxthreads, 1
+.cc_bottom sdram_block_read_PINOUT_V1_IS42S16400F.function
+
+.cc_top sdram_short_block_read_PINOUT_V1_IS42S16400F.function
.align 4
.globl sdram_short_block_read_PINOUT_V1_IS42S16400F
.type sdram_short_block_read_PINOUT_V1_IS42S16400F, @function
@@ -241,3 +248,4 @@ sdram_short_block_read_PINOUT_V1_IS42S16400F:
.globl sdram_short_block_read_PINOUT_V1_IS42S16400F.maxthreads
.linkset sdram_short_block_read_PINOUT_V1_IS42S16400F.maxthreads, 1
+.cc_bottom sdram_short_block_read_PINOUT_V1_IS42S16400F.function
@@ -132,6 +132,7 @@ void sdram_short_block_read_PINOUT_V1_IS42S16400F(unsigned buffer, unsigned word
* These numbers are tuned for 62.5MIPS.
*/
#define WRITE_SETUP_LATENCY (50)
+#define WRITE_COL_SETUP_LATENCY (50)
#define READ_SETUP_LATENCY (50)
static unsigned bank_table[SDRAM_BANK_COUNT_PINOUT_V1_IS42S16400F] =
@@ -175,6 +176,32 @@ static inline void sdram_write_PINOUT_V1_IS42S16400F(unsigned row, unsigned col,
}
#pragma unsafe arrays
+static inline void sdram_col_write_PINOUT_V1_IS42S16400F(unsigned bank, unsigned row, unsigned col,
+ short data, struct sdram_ports_PINOUT_V1_IS42S16400F &ports) {
+ unsigned t;
+ unsigned data_stop;
+ unsigned rowcol;
+
+ if(SDRAM_EXTERNAL_MEMORY_ACCESSOR)
+ if (col)
+ col = col - 1;
+ else
+ col = (SDRAM_COL_COUNT_PINOUT_V1_IS42S16400F - 1);
+
+ rowcol = (col << 16) | row | bank_table[bank];
+ data_stop = (0xffff << 16) | data;
+ t = partout_timestamped(ports.cas, 1, CTRL_WE_NOP);
+
+ t += 50;
+
+ partout_timed(ports.cas, 6, CTRL_CAS_ACTIVE | (CTRL_CAS_WRITE<<1) | (CTRL_CAS_NOP<<2) | (CTRL_CAS_TERM<<3) | (CTRL_CAS_PRECHARGE<<4) | (CTRL_CAS_NOP<<5), t);
+ partout_timed(ports.ras, 6, CTRL_RAS_ACTIVE | (CTRL_RAS_WRITE<<1) | (CTRL_RAS_NOP<<2) | (CTRL_RAS_TERM<<3) | (CTRL_RAS_PRECHARGE<<4) | (CTRL_RAS_NOP<<5), t);
+ partout_timed(ports.we , 6, CTRL_WE_ACTIVE | (CTRL_WE_WRITE<<1) | (CTRL_WE_NOP<<2) | (CTRL_WE_TERM<<3) | (CTRL_WE_PRECHARGE<<4) | (CTRL_WE_NOP<<5) , t);
+ ports.dq_ah @ t<: rowcol;
+ ports.dq_ah <: data_stop;
+}
+
+#pragma unsafe arrays
static inline void sdram_read_PINOUT_V1_IS42S16400F(unsigned row, unsigned col, unsigned bank,
unsigned buffer, unsigned word_count, struct sdram_ports_PINOUT_V1_IS42S16400F &ports) {
unsigned t, stop_time, jump, rowcol;
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