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/*
* ARMv8 Foundation model DTS
*/
#include <dt-bindings/interrupt-controller/arm-gic.h>
/memreserve/ 0x80000000 0x00020000;
/memreserve/ 0x80800000 0x01000000;
/ {
model = "Foundation-v8A";
compatible = "arm,foundation-aarch64", "arm,foundation-v8";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
chosen {
initrd-start = <0x0 0x80800000>;
initrd-end = <0x0 0x81800000>;
};
aliases { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu@0 {
device_type = "cpu";
compatible = "arm,armv8";
model = "Cortex-A57";
reg = <0x0 0x0>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,armv8";
model = "Cortex-A57";
reg = <0x0 0x1>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@2 {
device_type = "cpu";
compatible = "arm,armv8";
model = "Cortex-A57";
reg = <0x0 0x2>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
cpu@3 {
device_type = "cpu";
compatible = "arm,armv8";
model = "Cortex-A57";
reg = <0x0 0x3>;
enable-method = "spin-table";
cpu-release-addr = <0x0 0x8000fff8>;
};
};
memory {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x20000000>; /* 512 MB */
};
gen-timer { /* Generic Timer */
compatible = "arm,armv8-timer";
clock-frequency = <100000000>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>;
};
motherboard {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
eth0 { /* SMSC 91C111 ethernet */
compatible = "smc91x";
reg = <0x1a000000 0x10000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
switch = "br0";
};
gpio-leds { /* LEDs */
compatible = "bgpio,generic";
reg-names = "dat";
reg = <0x1c010008 0x4>;
};
SERIAL0: uart0 { /* PL011 serial port */
compatible = "arm,pl011";
reg = <0x1c090000 0x1000>;
clock-frequency = <24000000>;
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
};
SERIAL1: uart1 { /* PL011 serial port */
compatible = "arm,pl011";
reg = <0x1c0a0000 0x1000>;
clock-frequency = <24000000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
SERIAL2: uart2 { /* PL011 serial port */
compatible = "arm,pl011";
reg = <0x1c0b0000 0x1000>;
clock-frequency = <24000000>;
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
SERIAL3: uart3 { /* PL011 serial port */
compatible = "arm,pl011";
reg = <0x1c0c0000 0x1000>;
clock-frequency = <24000000>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
virtio_block {
compatible = "virtio,mmio";
reg = <0x1c130000 0x200>;
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
};
RTC0: rtc { /* PL031 real-time clock */
compatible = "arm,pl031";
reg = <0x1c170000 0x1000>;
clocks = <&v2m_clk24mhz>;
clock-names = "apb_pclk";
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
};
clcd {
compatible = "arm,pl111";
reg = <0x1c1f0000 0x1000>;
clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
clock-names = "clcdclk", "apb_pclk";
use_dma = <0>;
framebuffer = <0x18000000 0x00180000>;
};
};
clocks {
#address-cells = <1>;
#size-cells = <0>;
v2m_clk24mhz: clk24mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <24000000>;
clock-output-names = "v2m:clk24mhz";
};
v2m_refclk1mhz: refclk1mhz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <1000000>;
clock-output-names = "v2m:refclk1mhz";
};
v2m_refclk32khz: refclk32khz {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <32768>;
clock-output-names = "v2m:refclk32khz";
};
};
};