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[ARM] arm32ve: Make hypervisor ttbl walks and stage2 ttbl walks cache…

…able

Signed-off-by: Anup Patel <anup@brainfault.org>
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1 parent 883cd3e commit 21a867c13683ad7de53b55ed547aa9295785db53 @avpatel avpatel committed Jan 31, 2013
Showing with 8 additions and 0 deletions.
  1. +8 −0 arch/arm/cpu/arm32ve/cpu_entry_ttbl.c
@@ -153,6 +153,10 @@ _setup_initial_ttbl(virtual_addr_t load_start,
/* Setup Hypervisor Translation Control Register */
i = read_htcr();
i &= ~HTCR_T0SZ_MASK; /* Ensure T0SZ = 0 */
+ i &= ~HTCR_ORGN0_MASK; /* Clear ORGN0 */
+ i |= (0x3 << HTCR_ORGN0_SHIFT) & HTCR_ORGN0_MASK;
+ i &= ~HTCR_IRGN0_MASK; /* Clear IRGN0 */
+ i |= (0x3 << HTCR_IRGN0_SHIFT) & HTCR_IRGN0_MASK;
write_htcr(i);
/* Setup Hypervisor Translation Table Base Register */
@@ -164,5 +168,9 @@ _setup_initial_ttbl(virtual_addr_t load_start,
/* Setup Hypervisor Virtual Translation Control Register */
i = read_vtcr();
i |= (0x1 << VTCR_SL0_SHIFT) & VTCR_SL0_MASK;
+ i &= ~VTCR_ORGN0_MASK; /* Clear ORGN0 */
+ i |= (0x3 << VTCR_ORGN0_SHIFT) & VTCR_ORGN0_MASK;
+ i &= ~VTCR_IRGN0_MASK; /* Clear IRGN0 */
+ i |= (0x3 << VTCR_IRGN0_SHIFT) & VTCR_IRGN0_MASK;
write_vtcr(i);
}

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